- •Features
- •Memory
- •Peripherals
- •Table Of Contents
- •Revision History
- •General Description
- •Portable Low Power Architecture
- •System Integration
- •ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor Peripherals
- •Blackfin Processor Core
- •Memory Architecture
- •Internal (On-Chip) Memory
- •External (Off-Chip) Memory
- •I/O Memory Space
- •Booting
- •Event Handling
- •Core Event Controller (CEC)
- •System Interrupt Controller (SIC)
- •Event Control
- •DMA Controllers
- •Real-Time Clock
- •Watchdog Timer
- •Timers
- •Serial Ports (SPORTs)
- •Serial Peripheral Interface (SPI) Port
- •UART Port
- •General-Purpose I/O Port F
- •Parallel Peripheral Interface
- •General-Purpose Mode Descriptions
- •Input Mode
- •Frame Capture Mode
- •Output Mode
- •ITU-R 656 Mode Descriptions
- •Active Video Only Mode
- •Vertical Blanking Interval Mode
- •Entire Field Mode
- •Dynamic Power Management
- •Power Savings
- •Voltage Regulation
- •Voltage Regulator Layout Guidelines
- •Clock Signals
- •Booting Modes
- •Instruction Set Description
- •Development Tools
- •EZ-KIT Lite Evaluation Board
- •Designing an Emulator-Compatible Processor Board
- •Related Documents
- •Pin Descriptions
- •Specifications
- •Operating Conditions
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •Package Information
- •ESD Sensitivity
- •Timing Specifications
- •Clock and Reset Timing
- •Asynchronous Memory Read Cycle Timing
- •Asynchronous Memory Write Cycle Timing
- •SDRAM Interface Timing
- •External Port Bus Request and Grant Cycle Timing
- •Parallel Peripheral Interface Timing
- •Serial Ports
- •General-Purpose I/O Port F Pin Cycle Timing
- •Timer Cycle Timing
- •JTAG Test and Emulation Port Timing
- •Output Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Enable Time Measurement
- •Output Disable Time Measurement
- •Example System Hold Time Calculation
- •Capacitive Loading
- •Environmental Conditions
- •160-Ball BGA Ball Assignment
- •169-Ball PBGA ball assignment
- •176-Lead LQFP Pinout
- •Outline Dimensions
- •Surface Mount Design
- •Ordering Guide
OUTPUT DRIVE CURRENTS
Figure 30 through Figure 41 show typical current-voltage char acteristics for the output drivers of the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor. The curves represent the current drive capability of the output drivers as a function of output voltage.
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150 |
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VDDEXT = 2.75V |
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100 |
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VDDEXT = 2.50V |
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VDDEXT |
= 2.25V |
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50 |
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CURRENT |
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VOH |
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SOURCE |
–50 |
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–100 |
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–150 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
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0 |
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SOURCE VOLTAGE (V)
Figure 30. Drive Current A (VDDEXT = 2.5 V)
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60 |
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VDDEXT = 1.9V |
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VDDEXT = 1.8V |
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(mA) |
40 |
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VDDEXT = 1.7V |
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–20 |
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–40 |
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–60 |
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–80 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
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SOURCE VOLTAGE (V)
Figure 31. Drive Current A (VDDEXT = 1.8 V)
ADSP-BF531/ADSP-BF532/ADSP-BF533 |
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150 |
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VDDEXT = 3.65V |
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100 |
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VDDEXT = 3.30V |
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VDDEXT = 2.95V |
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(mA) |
50 |
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CURRENT |
0 |
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VOH |
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SOURCE |
–50 |
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–100 |
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VOL |
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–150 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
3.5 |
SOURCE VOLTAGE (V)
Figure 32. Drive Current A (VDDEXT = 3.3 V)
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150 |
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100 |
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VDDEXT = 2.75V |
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VDDEXT = 2.50V |
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(mA) |
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VDDEXT = 2.25V |
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50 |
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CURRENT |
0 |
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VOH |
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SOURCE |
–50 |
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–100 |
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VOL |
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–150 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
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0 |
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SOURCE VOLTAGE (V)
Figure 33. Drive Current B (VDDEXT = 2.5 V)
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60 |
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VDDEXT = 1.9V |
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VDDEXT = 1.8V |
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(mA) |
40 |
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VDDEXT = 1.7V |
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–20 |
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–40 |
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–60 |
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–800 |
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0.5 |
1.0 |
1.5 |
2.0 |
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SOURCE VOLTAGE (V) |
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Figure 34. Drive Current B (VDDEXT = 1.8 V)
Rev. E | Page 43 of 60 | July 2007
ADSP-BF531/ADSP-BF532/ADSP-BF533 |
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150 |
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VDDEXT = 3.65V |
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100 |
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VDDEXT = 3.30V |
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VDDEXT = 2.95V |
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(mA) |
50 |
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CURRENT |
0 |
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VOH |
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SOURCE |
–50 |
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–100 |
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VOL |
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–150 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
3.5 |
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SOURCE VOLTAGE (V) |
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Figure 35. Drive Current B (VDDEXT = 3.3 V)
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60 |
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VDDEXT = 2.75V |
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40 |
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VDDEXT = 2.50V |
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VDDEXT = 2.25V |
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20 |
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(mA) |
0 |
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CURRENT |
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VOH |
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–20 |
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SOURCE |
–40 |
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VOL |
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–60 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
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0 |
SOURCE VOLTAGE (V)
Figure 36. Drive Current C (VDDEXT = 2.5 V)
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30 |
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VDDEXT = 1.9V |
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20 |
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VDDEXT = 1.8V |
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VDDEXT = 1.7V |
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(mA) |
10 |
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CURRENT |
0 |
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OURCES |
–10 |
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–20 |
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–30 |
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–40 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
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SOURCE VOLTAGE (V)
Figure 37. Drive Current C (VDDEXT = 1.8 V)
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80 |
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VDDEXT = 3.65V |
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VDDEXT = 3.30V |
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60 |
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VDDEXT = 2.95V |
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(mA) |
40 |
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20 |
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CURRENT |
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0 |
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VOH |
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–20 |
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SOURCE |
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–40 |
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–60 |
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VOL |
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–80 |
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–100 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
3.5 |
SOURCE VOLTAGE (V)
Figure 38. Drive Current C (VDDEXT = 3.3 V)
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80 |
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VDDEXT = 2.75V |
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VDDEXT = 2.50V |
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60 |
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VDDEXT = 2.25V |
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(mA) |
40 |
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CURRENT |
20 |
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VOH |
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SOURCE |
–20 |
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–40 |
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–60 |
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–80 |
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–100 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
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0 |
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SOURCE VOLTAGE (V)
Figure 39. Drive Current D (VDDEXT = 2.5 V)
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40 |
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VDDEXT = 1.9V |
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VDDEXT |
= 1.8V |
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(mA) |
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VDDEXT = 1.7V |
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20 |
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CURRENT |
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0 |
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OURCES |
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–20 |
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–40 |
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–60 |
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0.5 |
1.0 |
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2.0 |
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SOURCE VOLTAGE (V)
Figure 40. Drive Current D (VDDEXT = 1.8 V)
Rev. E | Page 44 of 60 | July 2007
