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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / ADSP-BF531_BF532_BF533.pdf

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ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Ports

Table 22 through Table 25 on Page 35 and Figure 22 on Page 35 through Figure 23 on Page 36 describe Serial Port operations.

Table 22. Serial Ports—External Clock

					VDDEXT = 1.8 V		VDDEXT = 2.5 V/3.3 V
Parameter				Min		Max	Min	Max	Unit
Timing Requirements
tSFSE	TFSx/RFSx Setup Before TSCLKx/RSCLKx1			3.0			3.0		ns
tHFSE	TFSx/RFSx Hold After TSCLKx/RSCLKx1			3.0			3.0		ns
tSDRE	Receive Data Setup Before RSCLKx1			3.0			3.0		ns
tHDRE	Receive Data Hold After RSCLKx1			3.0			3.0		ns
tSCLKEW	TSCLKx/RSCLKx Width			8.0			4.5		ns
tSCLKE	TSCLKx/RSCLKx Period			20.0			15.02		ns
Switching Characteristics
tDFSE	TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3					10.0		10.0	ns
tHOFSE	TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1			0.0			0.0		ns
tDDTE	Transmit Data Delay After TSCLKx1					10.0		10.0	ns
tHDTE	Transmit Data Hold After TSCLKx1			0.0			0.0		ns
1 Referenced to sample edge.
2 For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3 Referenced to drive edge.
Table 23. Serial Ports—Internal Clock

		VDDEXT = 1.8 V			VDDEXT = 1.8 V		VDDEXT = 2.5 V/3.3 V
		LQFP/PBGA			MBGA Package		All Packages
		Packages
Parameter		Min	Max		Min	Max	Min	Max	Unit
Timing Requirements
tSFSI	TFSx/RFSx Setup Before TSCLKx/RSCLKx1	11.0			11.0		9.0		ns
tHFSI	TFSx/RFSx Hold After TSCLKx/RSCLKx1	−2.0			−2.0		−2.0		ns
tSDRI	Receive Data Setup Before RSCLKx1	9.5			9.0		9.0		ns
tHDRI	Receive Data Hold After RSCLKx1	0.0			0.0		0.0		ns
tSCLKEW	TSCLKx/RSCLKx Width	4.5			4.5		4.5		ns
tSCLKE	TSCLKx/RSCLKx Period	20.0			15.0		15.0		ns
Switching Characteristics
tDFSI	TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2		3.0			3.0		3.0	ns
tHOFSI	TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1	−1.0			−1.0		−1.0		ns
tDDTI	Transmit Data Delay After TSCLKx1		3.0			3.0		3.0	ns
tHDTI	Transmit Data Hold After TSCLKx1	−2.5			−2.0		−2.0		ns
tSCLKIW	TSCLKx/RSCLKx Width	6.0			6.0		4.5		ns

1 Referenced to sample edge.

2 Referenced to drive edge.

Rev. E | Page 34 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

DATA RECEIVE—INTERNAL CLOCK

DRIVE		SAMPLE
EDGE		EDGE
	tSCLKIW
RSCLKx
	tDFSI
tHOFSI	tSFSI	tHFSI
RFSx
	tSDRI	tHDRI
DRx

DATA RECEIVE—EXTERNAL CLOCK

DRIVE		SAMPLE
EDGE		EDGE
	tSCLKEW
RSCLKx
	tDFSE
tHOFSE	tSFSE	tHFSE
RFSx
	tSDRE	tHDRE
DRx

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE		SAMPLE
EDGE		EDGE
	tSCLKIW
TSCLKx
	tDFSI
tHOFSI	tSFSI	tHFSI
TFSx
	tDDTI
tHDTI
DTx

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE		SAMPLE
EDGE		EDGE
	tSCLKEW
TSCLKx
	tDFSE
tHOFSE	tSFSE	tHFSE
TFSx
	tDDTE
tHDTE
DTx

	NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
	Figure 22.	Serial Ports
Table 24. Serial Ports—Enable and Three-State

				VDDEXT = 1.8 V	VDDEXT = 2.5 V/3.3 V
Parameter			Min	Max	Min	Max	Unit
Switching Characteristics
tDTENE	Data Enable Delay from External TSCLKx1		0		0		ns
tDDTTE	Data Disable Delay from External TSCLKx1			10.0		10.0	ns
tDTENI	Data Enable Delay from Internal TSCLKx1		−2.0		−2.0		ns
tDDTTI	Data Disable Delay from Internal TSCLKx1			3.0		3.0	ns

1	Referenced to drive edge.
Table 25. External Late Frame Sync

			VDDEXT = 1.8 V		VDDEXT = 1.8 V	VDDEXT = 2.5 V/3.3 V
		LQFP/PBGA Packages		MBGA Package			All Packages
Parameter		Min	Max	Min	Max	Min	Max	Unit
Switching Characteristics
tDDTLFSE Data Delay from Late External TFSx or External RFSx			10.5		10.0		10.0	ns
	with MCE = 1, MFD = 01, 2
tDTENLFS Data Enable from Late FS or MCE = 1, MFD = 01, 2		0		0		0		ns
1	MCE = 1, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE.
2	If external RFSx/TFSx setup to RSCLKx/TSCLK x> tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.

Rev. E | Page 35 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

EXTERNAL RFSx WITH MCE = 1, MFD = 0
DRIVE	SAMPLE	DRIVE

RSCLKx	tSFSE/I	tHOFSE/I
	tSFSE/I	tHOFSE/I
RFSx
	tDTENLFS	tDDTTE/I
	tDTENLFS	tDTENE/I
		tDTENE/I

DTx

1ST BIT

2ND BIT

tDDTLFSE

LATE EXTERNAL TFSx
DRIVE	SAMPLE	DRIVE
TSCLKx		tHOFSE/I
tSFSE/I
TFSx
tDTENLFS		tDDTTE/I
tDTENLFS		tDTENE/I
		tDTENE/I
DTx	1ST BIT	2ND BIT
tDDTLFSE

Figure 23. External Late Frame Sync

Rev. E | Page 36 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Peripheral Interface (SPI) Port

—Master Timing

Table 26 and Figure 24 describe SPI port master operations.

Table 26. Serial Peripheral Interface (SPI) Port—Master Timing

					VDDEXT = 1.8 V		VDDEXT = 1.8 V		VDDEXT = 2.5 V/3.3 V
					LQFP/PBGA Packages		MBGA Package		All Packages
Parameter					Min	Max	Min	Max	Min	Max	Unit
Timing Requirements
tSSPIDM	Data Input Valid to SCK Edge (Data Input Setup)				10.5		8.5		7.5		ns
tHSPIDM	SCK Sampling Edge to Data Input Invalid				–1.5		–1.5		–1.5		ns
Switching Characteristics
tSDSCIM		Low to First SCK Edge			2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSDSCIM	SPISELx	Low to First SCK Edge			2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPICHM	Serial Clock High Period				2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPICLM	Serial Clock Low Period				2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPICLK	Serial Clock Period				4tSCLK –1.5		4tSCLK –1.5		4tSCLK –1.5		ns
tHDSM	Last SCK Edge to			High	2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tHDSM	Last SCK Edge to		SPISELx	High	2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPITDM	Sequential Transfer Delay				2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay)					0	6	0	6	0	6	ns
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold)					–1.0	+4.0	–1.0	+4.0	–1.0	+4.0	ns

SPISELx
(OUTPUT)
tSDSCIM	tSPICHM	tSPICLM	tSPICLK	tHDSM	tSPITDM

SCK (CPOL = 0) (OUTPUT)

		tSPICLM	tSPICHM
	SCK
	(CPOL = 1)
	(OUTPUT)
			tDDSPIDM	tHDSPIDM
	MOSI		MSB		LSB
	(OUTPUT)		MSB		LSB
	(OUTPUT)
CPHA = 1		tSSPIDM	tHSPIDM	tSSPIDM	tHSPIDM
	MISO	MSB VALID		LSB VALID
	(INPUT)	MSB VALID		LSB VALID
	(INPUT)
			tDDSPIDM	tHDSPIDM
	MOSI	MSB		LSB
	(OUTPUT)	MSB		LSB
	(OUTPUT)
CPHA = 0	tSSPIDM	tHSPIDM
	tSSPIDM	tHSPIDM
	MISO	MSB VALID		LSB VALID
	(INPUT)	MSB VALID		LSB VALID
	(INPUT)

Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. E | Page 37 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

Serial Peripheral Interface (SPI) Port

—Slave Timing

Table 27 and Figure 25 describe SPI port slave operations.

Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing

					VDDEXT = 1.8 V		VDDEXT = 1.8 V		VDDEXT = 2.5 V/3.3 V
					LQFP/PBGA Packages		MBGA Package		All Packages
Parameter					Min	Max	Min	Max	Min	Max	Unit
Timing Requirements
tSPICHS Serial Clock High Period					2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPICLS	Serial Clock Low Period				2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPICLK	Serial Clock Period				4tSCLK –1.5		4tSCLK –1.5		4tSCLK –1.5		ns
tHDS	Last SCK Edge to			Not Asserted	2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tHDS	Last SCK Edge to		SPISS	Not Asserted	2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSPITDS	Sequential Transfer Delay				2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSDSCI		Assertion to First SCK Edge			2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSDSCI	SPISS	Assertion to First SCK Edge			2tSCLK –1.5		2tSCLK –1.5		2tSCLK –1.5		ns
tSSPID	Data Input Valid to SCK Edge (Data Input Setup)				1.6		1.6		1.6		ns
tHSPID	SCK Sampling Edge to Data Input Invalid				1.6		1.6		1.6		ns
Switching Characteristics
tDSOE		Assertion to Data Out Active			0	10	0	9	0	8	ns
tDSOE	SPISS	Assertion to Data Out Active			0	10	0	9	0	8	ns
tDSDHI		Deassertion to Data High Impedance			0	10	0	9	0	8	ns
tDSDHI	SPISS	Deassertion to Data High Impedance			0	10	0	9	0	8	ns
tDDSPID SCK Edge to Data Out Valid (Data Out Delay)					0	10	0	10	0	10	ns
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold)					0	10	0	10	0	10	ns

SPISS
(INPUT)
	tSPICHS	tSPICLS	tSPICLK	tHDS	tSPITDS
			tSPICLK	tHDS	tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI	tSPICLS	tSPICHS
SCK
(CPOL = 1)
(INPUT)
tDSOE	tDDSPID
	tDDSPID	tHDSPID	tDDSPID	tDSDHI
		tHDSPID	tDDSPID	tDSDHI
MISO		MSB		LSB
(OUTPUT)		MSB		LSB
(OUTPUT)
CPHA = 1	tSSPID	tHSPID	tSSPID	tHSPID
CPHA = 1	tSSPID	tHSPID
MOSI	MSB VALID			LSB VALID
(INPUT)	MSB VALID			LSB VALID
(INPUT)
tDSOE	tDDSPID			tDSDHI
MISO	MSB		LSB
(OUTPUT)	MSB		LSB
(OUTPUT)
CPHA = 0			tSSPID	tHSPID
CPHA = 0

MOSI	MSB VALID		LSB VALID
(INPUT)	MSB VALID		LSB VALID
(INPUT)

Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. E | Page 38 of 60 | July 2007

ADSP-BF531/ADSP-BF532/ADSP-BF533

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing

Figure 26 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 26 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.

CLKOUT

(SAMPLE CLOCK)

Rx	DATA[8:5]

RECEIVE

INTERNAL

UART RECEIVE

INTERRUPT

	START
Tx	DATA[8:5]
	DATA[8:5]

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

STOP

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

STOP[2:1]

UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT

Figure 26. UART Port—Receive and Transmit Timing

Rev. E | Page 39 of 60 | July 2007

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