TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
TIMING DIAGRAMS
This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner of page for the specific device.
Timing measurements are referenced to and from a low voltage of 0.8 voltage and a high voltage of 2 volts, unless otherwise noted.
clock timing
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tc(CI) |
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tf(CI) |
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tr(CI) |
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X/2CLKIN |
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th(S) |
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tw(CIH) |
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tw(CIL) |
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tsu(S) |
tsu(S) |
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SYNC |
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tc(C) |
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td(CIH-C) |
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tw(CL) |
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td(CIH-C) |
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CLKOUT1 |
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tw(CH) |
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td(CIH-C) |
tr(C) |
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tf(C) |
STRB |
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td(CIH-C) |
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tc(C) |
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tw(CL) |
CLKOUT2 |
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td(C1-C2) |
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td(C1-C2) |
tf(C) |
tr(C) |
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td(C1-C2) |
tw(CH) |
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td(C1-C2) |
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INFORMATION ADVANCE
TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
memory read timing
td(C1-S) |
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CLKOUT1 |
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td(C1-S) |
CLKOUT2 |
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td(C2-S) |
td(C2-S) |
STRB |
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tw(SH) |
tsu(A) |
th(A) |
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tw(SL) |
A15-A0, |
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BR, PS, DS |
Valid |
or IS |
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ta(A) |
R/W |
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td(SL-R) |
tsu(D)R |
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READY |
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th(SL-R) |
th(D)R |
D15-D0 |
Data In |
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TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
memory write timing
CLKOUT1
CLKOUT2
STRB
th(A)
tsu(A)
A15-A0,
BR, PS, DS Valid or IS
R/W
READY |
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tsu(D)W |
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th(D)W |
D15-D0 |
Data Out |
ten(D) |
tdis(D) |
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TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
one wait-state memory access timing
CLKOUT1
CLKOUT2
STRB |
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A15-A0, BR, |
th(C2H-R) |
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PS, DS, R/W or |
Valid |
IS |
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th(C2H-R) |
td(C2H-R) |
td(C2H-R) |
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READY |
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td(M-R) |
th(M-R) |
th(M-R) |
td(M-R) |
D15-D0 |
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(For Read |
Data In |
Operation) |
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D15-D0 |
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(For Write |
Data Out |
Operation) |
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td(MSC) |
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td(MSC) |
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MSC |
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TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
reset timing
CLKOUT1 |
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tsu(IN) |
td(RS) |
tsu(IN) |
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th(IN) |
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RS |
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tw(RS) |
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A15-A0 |
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Valid |
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Fetch |
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Location 0 |
D15-D0 |
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Valid |
Begin |
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Program |
PS |
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Execution |
STRB
Control
Signals²
IACK 
Serial Port
Control³
² Control signals are DS, IS, R/W, and XF. ³ Serial port controls are DX and FSX.
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TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
interrupt timing (TMS32020)
CLKOUT1 |
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STRB |
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tsu(IN) |
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th(IN) |
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tw(IN) |
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INT2-INT0 |
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tf(IN) |
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td(IACK) |
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A15-A0 |
FETCH N |
FETCH N + 1 |
FETCH I |
FETCH I + 1 |
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td(IACK) |
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IACK |
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interrupt timing (TMS320C25)
CLKOUT1 |
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tsu(IN) |
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STRB |
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th(IN) |
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tw(IN) |
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INT2-INT0 |
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tf(IN) |
td(IACK) |
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A15-A0 |
FETCH N |
FETCH N + 1 |
FETCH N + 2 |
N + 3 |
FETCH I |
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td(IACK) |
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IACK |
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TMS320 SECOND-GENERATION
DEVICES
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
serial port receive timing
tc(SCK)
tr(SCK)
tw(SCK)
CLKR
th(DR) |
tf(SCK) |
th(FS) |
tw(SCK) |
FSR
tsu(FS)
tsu(DR)
DR
serial port transmit timing
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tc(SCK) |
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tw(SCK) |
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tr(SCK) |
CLKX |
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td(CH-DX) |
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tf(SCK) |
tw(SCK) |
th(FS) |
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FSX |
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(Input, |
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TXM = 0) |
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tsu(FS) |
td(FL-DX) |
td(CH-DX) |
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DX |
N = 1 |
N = 8,16 |
td(CH-FS) |
td(CH-FS) |
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FSX |
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(Output, |
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TXM = 1) |
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TMS32020
INFORMATION ADVANCE
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
BIO timing
CLKOUT1 |
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STRB |
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FETCH Branch Address |
FETCH Next Instruction |
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A15-A0 |
FETCH |
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BIOZ |
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PC = N |
PC = N + 1 |
PC = N + 2 |
PC = N + 3 |
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tsu(IN) |
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or Branch Address |
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th(IN) |
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BIO |
Valid |
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external flag timing
CLKOUT1
STRB |
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td(XF) |
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A15-A0 |
Valid |
FETCH |
Valid |
Valid |
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SXF/RXF |
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PC = N ± 1 |
PC = N |
PC = N + 1 |
PC = N + 2 |
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XF |
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Valid |
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TMS320C25
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SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990 |
BIO timing |
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CLKOUT1 |
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STRB |
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FETCH Branch Address |
FETCH Next Instruction |
A15-A0 |
FETCH |
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BIOZ |
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PC = N |
PC = N + 1 |
PC = N + 2 |
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tsu(IN) |
or Branch Address |
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th(IN) |
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BIO |
Valid |
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external flag timing
CLKOUT1
STRB |
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td(XF) |
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A15-A0 |
FETCH |
Valid |
Valid |
Valid |
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SXF/RXF |
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PC = N |
PC = N + 1 |
PC = N + 2 |
PC = N + 3 |
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XF |
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Valid |
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TMS32020
INFORMATION ADVANCE
SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
HOLD timing (part A)
CLKOUT1 |
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CLKOUT2 |
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STRB |
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td(C2H-H)² |
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HOLD |
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A15-A0 |
N |
N + 1 |
N + 2 |
PS, DS, |
Valid |
Valid |
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or IS |
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R/W |
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tdis(C1L-A) |
D15-D0 |
In |
In |
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tdis(AL-A) |
HOLDA
td(C1L-AL)
N |
N + |
1 |
N/A |
N/A |
FETCH |
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N ± 1 |
N |
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Dummy |
Dead |
EXECUTE |
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²HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
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