Учебники / 0841558_16EA1_federico_milano_power_system_modelling_and_scripting

Fig. 19.1 SVC schemes: (a) firing angle model and (b) equivalent susceptance model

vref

αmin

Fig. 19.2 SVC Type I control diagram

The state variable α undergoes an anti-windup limiter which indirectly allows limiting the SVC current. Table 19.1 defines all parameters of the SVC Type I.

19.1.2SVC Type II

A common approximation consists in assuming that the controlled variable is bSVC and not the firing angle α (see Figure 19.1.b). The simplified control scheme is depicted in Figure 19.3 and undergoes the following di erential equation:

vref bminSVC

Fig. 19.3 SVC Type II control diagram

The model is completed by the algebraic equation expressing the reactive power injected at the SVC node:

The regulator has an anti-windup limiter, i.e., the reactance bSVC is locked if one of its limits is reached. Table 19.2 reports data and control parameters for the SVC type 2.

19.1.3SVC Initialization

Although there is no particular issue in including the detailed SVC model into the power flow analysis, SVC devices are typically initialized after power flow analysis. To impose the voltage regulation a PV generator with p0G = 0 can be used. The only di erence is that the reactive power limits of the PV generator do not coincide exactly with the susceptance limits of the SVC device, in fact, qGmax = bmaxSVCvh2 only for the nominal value of the bus voltage.

Fig. 19.4 Comparison of SVC models for the IEEE 14-bus system

Example 19.1 Comparison of SVC Models

Figure 19.4 shows a comparison of the transient response of the SVC models Type I and II described above. The plot was obtained substituting the static shunt admittance at bus 9 of the IEEE 14-bus system for an SVC device. All SVC data are given in Appendix D. The reference voltage of SVC regulators is vref = 1.0563 pu, i.e., the same voltage value as obtained by the power flow analysis using the static shunt admittance. The regulators of both SVC models improve the voltage profile at bus 9. SVC Type II shows a zero static error (due to the integral regulator) but presents high-frequency oscillations.

19.2Thyristor Controlled Series Compensator

The Thyristor Controlled Series Compensator (TCSC) allows varying the series reactance of a transmission line and, thus, regulating the active flow through the transmission line itself. The functioning of the TCSC is similar to the SVC, but for the fact that the TCSC is a series device, as shown in Figure 19.5.

α

Fig. 19.5 TCSC schemes: (a) firing angle model and (b) equivalent susceptance model

The regulated variable is the firing angle α. The equivalent series reactance in balanced, fundamental frequency conditions is [129]:

− π cos kx(π − α) − 2kx4α cos kx(π − α)

+2αkx2 cos kx(π − α) − kx4 sin 2α cos kx(π − α)

+kx2 sin 2α cos kx(π − α) − 4kx3 cos2 α sin kx(π − α)

− 4kx2 cos α sin α cos kx(π − α) /[π(kx4 − 2kx2 + 1) cos kx(π − α)]

The model (19.7) can show numerical issues in case xTCSC(α) = 0.

Since the TCSC device is always connected in series with a transmission line, another common model considers the series of the TCSC and the transmission line as an unique device. Assuming a loss-less line and that the series reactance of the line is xhk , the resulting power flow equations are:

This model also allows removing numerically issues of (19.7) of xTCSC(α) if

|xminTCSC| < xhk .

Fig. 19.6 TCSC control diagram

A common control scheme for TCSC devices is shown in Figure 19.6 and works for regulating both the firing angle α and the reactance xTCSC. The DAE system is as follows:

where all parameters are defined in Table 19.3. The output signal of the leadlag block can be either the firing angle α or, using a simplified model, the reactance xTCSC. Considering the firing angle, one has:

If using the reactance xTCSC, equation (19.12) and the control scheme of Figure 19.6 are still valid but substituting α with xTCSC.

19.3.1Detailed Model

The detailed model consists of a shunt-connected VSC device with a capacitor in the dc side. The model is composed of three parts, namely the dc network, the VSC and the controllers.

Dc network : The dc side is a parallel RC defined by (17.10) and (17.2). Furthermore, the dc network must contain two nodes, one of which is connected to the ground. The VSC and the RC element are connected in parallel to the dc nodes.

Shunt-connected VSC model : The equations of the VSC are (17.2) and (18.9)- (18.12).

Regulators: The ac voltage control is obtained regulating the modulating amplitude am [322]:

whereas the dc voltage control is regulated through the firing angle α:

Finally, low pass filters are used for modelling both the ac and dc voltage measurements:

Voltage and modulating amplitude controls along with the measurement transfer functions are depicted in Figure 19.8. Both the ac and dc voltage controls undergo a windup limiter. For the dc voltage control, the limits on α can be computed imposing the power balance:

where gT + jbT = 1/(rT + jxT ) is the impedance of the VSC embedded = vdcref and vh = vacref, from (19.16) it can be

vdcref

αmin

Fig. 19.8 STATCOM ac and dc voltage control diagrams

where

Finally, the limits for the firing angle α are computed imposing in the equation (19.17) the limits imax and imin. Table 19.4 defines all parameters required by STATCOM regulators.

19.3.2Simplified Dynamic Model

A simplified STATCOM current injection model has been proposed in [61, 122, 252]. The STATCOM current ish is always kept in quadrature in relation to the bus voltage so that only reactive power is exchanged between the ac system and the STATCOM. The equivalent circuit and the control scheme are shown in Figure 19.9. The di erential equation and the reactive power injected at the STATCOM node are, respectively:

qh = ishvh

Fig. 19.9 STATCOM circuit and control diagram

where all parameters are defined in Table 19.5. The current ish undergoes an anti-windup limiter.

19.3.3Power Flow Model

The STATCOM power flow model is simply obtained based on the power flow model of the VSC device (18.27) and (18.28). In particular, (18.28) are:

The latter condition is satisfied only if the current ish ≤ imaxsh .