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Национальный исследовательский университет «МИЭТ»

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Chung-Yu Wu - Analog Circuit Design

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<<< < Предыдущая 7 8 9 10 11 12 13 14 15 16 17 1819 / 4919 20 21 22 23 24 25 26 27 28 29 30 31 > Следующая >>>

+VDD

VBIAS

+
Vin	C	L	- V	out +
-		L		out +
-				CL	CMFB
				CL	CMFB

-VSS

CMFB: Common-mode feedback circuitry

3.High-performance micropower fully differential OP AMP.

Simplified schematic of the class AB amplifier:

	A	+VDD
M17	M12	M11
M17			M14
BIAS3			BIAS1
M20			M16
M5	M1	M2	M6
Iin(+)			Iin(-)
OUT(+)			OUT(-)
M7			M8

	I1	I2	M4
	M3		M4	BIAS2
M19	BIAS4			BIAS2
M19	I		I	M15

M18

M10

M13

A -VSS

8 - 27

CHUNG-YU WU

+VDD

M17

BIAS3

M20		M5

Iin(+)

OUT(+)

4 μA	I	class AB	M7

3μA
2 μA		class A
1μA			I

-400 -200	200mV	400mV	Vin
	− 1μA		Vin

− 2μA

M12

Iin (-)

OUT(-)

BIAS2

M15

M13

-VSS

Active portion of the amplifier for a positive input signal.

Detailed schematic of the entire amplifier without CMFB:

			+VDD
	M23		M11		M14
	M23	M12			M14
		M12
M17
M20	M22			M27
	M5	M1	M2	M26	M16
	M5	M1	M2	M6
OUT(+)	Iin(+)			Iin(-)	OUT(-)
OUT(+)					OUT(-)
	M7	I2	I1	M8
		I2	I1

M19	M3	M4
	M24	M30	M15

	M60A
M18	M25
	M10
M21	M13
	M9
	-VSS

8 - 28

CHUNG-YU WU

*NMOS dynamically biased current mirror:

					I30			OUT
					I30
			M30				M15
				10			40
				10			10
			I9
M9							M	13
								13
	40						40
	10						10
							- VSS
If I9 = I30 ,		VGS 9		= VGS13	= VGS15
	VDS13			= VGS 30 -VGS9
Set	VDG13 = -VTH ÞVGS 30 = 2VGS 9 -VTH
Design	(W )		, such that		V	= 2V	-V
	L	30			GS 30	GS 9	TH
Þ M 13	is always sat. at the edge of the linear region.

Þ Output swing-

*Dynamic CMFB is used.

	AMPLIFIER DEVICE SIZES
DEVICE	Z(μm)	L(μm)

M1	180	6

M2	180	6

M3	140	6

M4	140	6

M5	150	6

M6	150	6

M7	200	6

M8	200	6

M9	22	10

M10	22	10

8 - 29

CHUNG-YU WU

M11	29	7

M12	29	7

M13	22	10

M14	29	7

M15	22	6

M16	29	6

M17	29	7

M18	22	10

M19	22	6

M20	29	6

M21	20	9

M22	6	12

M23	28	6

M24	6	14

M25	20	9

M26	6	12

M27	28	6

M30	6	14

AMPLIFIER SPECIFICATIONS

CORE AMPLIFIER SPECIFICATIONS

(0-5 Volts Supply)

100μW Quiescent Power Dissipation

DIFFERENTIAL GAIN	>10.000«
UNITY GAIN FREQUENCY	2 MHz«
NOISE	140 nV/	Hz	1KHz
	50 nV/	Hz	white
OUTPUT SWING	0.5 Volts from Supply«
AREA	300 mils2

«inferred from filter measurement Ref: IEEE JSSC, vol. SC-20, pp.1122-1132, Dec. 1985

8 - 30

CHUNG-YU WU

4.Fully differential class AB OP AMP with CMFB circuit

+ VDD

100μA

M18

M16

M15

M17

100μA

M20

BIAS

M19

MC1

MC2

Vin-

Vin+

MC12 MC11

out

MC4

MC5

MC15

MC14

BIAS

M14

BIAS

5μA

BIAS

M13

MC6

C17

M10

M11

C16

M12

- VSS

Characteristics:
Technology	: 5um, P-well CMOS, double-poly cap.
Open loop gian	: 1180	unity-gain freq	: 10Mhez
CMRR	: 61db	power consumption : 2.3mw
Area	: 290 mils2	power supply	: ± 5V

Ref: IEEE JSSC ,vol.sc-20 , pp.1103-1112 , Ddec,1985

8 - 31

CHUNG-YU WU

§8-5 Recent Design Examples of CMOS OP AMPs

§8-5.1 Fast-settling CMOS OP AMP for SC Circuit with 90-dB DC Gain

Reference : IEEE JSSC, vol.25, no.6, pp.1379-1384, Dec 1990.

1.Gain boosting

1)Cascode gain stage with gain enhancement

+VDD

Vref	+	Vo
Vref	+	Cload
	Aadd	Cload
	Aadd	M2
	_

-VSS

Rout = [g m 2ro2 ( Aadd + 1) + 1]ro1 + ro 2

Atot = g m1ro1[g m 2ro 2 ( Aadd + 1) + 1]

Aorig = g m1 g m2 ro1ro 2

2) Repetitive implementation of gain enhancement +VDD

-VSS

2.High-frequency behavior

ω4 is

Aadd

	gain (log)
	gain (log)
Atot
		gain enhancement
		gain enhancement
Aadd		= Aadd(0) +1

Aorig

ω (log) ω6

ω1 ω2

ω3 ω4 ω5

8 - 32

CHUNG-YU WU

ω3 : Upper 3-dB frequency of		Aorig
ω5 : Unity-gain frequency of		Atot
ω2	:Upper 3-dB frequency of	Aadd
ω4	:Unity-gain frequency of	Aadd
ω1 : Upper 3-dB frequency of		Atot
ω5	: Unity-gain frequency of	Aorig

We want ω5 Aorig =ω5 Atot

ω2 > ω1 => The bandwidth is determined by ω1, i.e. Rout and Cload. => ω4 > ω3

But ω4 < ω5 for easy design of Aadd.

and M2 forms a close loop with the dominant pole of ω2 and the second pole at the source of M2, i.e. ω6

The stability consideration requires ω4 < ω6

=>The safe range of

ω3 < ω4 < ω6

*The repetitive usage of the gain-enhancement techniques yields a decoupling of the

op-amp gain and unity-gain frequency fu. That is:gain− without fu↓ .

3.Settling behavior

1. Total output impedance Ztot

Ztot= Zload // Zout

Zload: impedance of Cload

Zout: output impedance of the amplifier

Z load

Normalized impedance

Zout Zorig (Add+1)

g −1

(log)

Z tot

g m−1

Z out

g m−1

Zorig

gm−1

Pole-zero

ω (log)

doublet

ω1 ω

3 ω

4 ω

8 - 33

CHUNG-YU WU

ω2 : Upper-3dB freq. Of Aadd èthe same for Z out

ω4 : Unity-gain freq. Of Aadd

	For ω > ω4 , Aadd < 1èZ out → Zorig
	èA zero is formed at		ω4 for Z out
Z total	= Z load \|\| Z out èA pole-zero doublet is formed around ω4
		èThe same doublet of Atotal
3. Design technique for fast settling
The time constant of the doublet,			1		, must be smaller than the main close-loop time


				ωPZ
constant,	1	. where β is the feedback factor.

βωunity

The safe range for the		ω4 .
	gain (log)
	Aaddd
1/β	Aclosed-loop
1/β	ω2	βω5		ω4	ω5	ω6
	ω2	βω5		ω4	ω5	ω6
						ω (log)
			Safe range for ω4
	βω5 < ω4		< ω6
		doublet

4. CMOS OP AMP circuit

8 - 34

CHUNG-YU WU

+VDD

Vbp1		Vbp1

Vcm

Vin-	Vin+
	Ib
Vout+	Vout-
Vbn1	Vbn1

-VSS

MAIN CHARACTERISTICS OF THE OP AMP

Gain enh.	on	Off

DC-gain	90dB	46dB
Unity-gain freq.	116MHz	120MHz
Load cap.	16pF	16pF
Phase margin	64deg.	63deg
Power cons.	52mW	45mW
Output-swing	4.2V	4.2V
Supply voltage	5.0V	5.0V
Settling time	61.5ns	-
0.1% , Vo = 1V

§ 8-5.2 1V Rail-to-Rail CMOS OP AMPs

Ref.: IEEE JSSC vol.35, no.1, pp.33-44 Jan. 2000

	8 - 35
1. Typical input stage for rail-to-rail amplifiers	CHUNG-YU WU
1. Typical input stage for rail-to-rail amplifiers
* Parallel-connected complementary	* Operating zones for low VDD/VSS
differential pairs.

* Operating zones for extremely low VDD/VSS

Dead region.

Both pairs are off.

2. Dynamic level-shifting current		Vi,n,cm=Vi,cm+IR
	generator	Vi,p,cm=Vi,cmi-IR

*The input resistance over the entire voltage range is infinite and no loading effect or input current over the previous stage.

Usually mismatches cause negligible input current.

* The symmetrical topology ensures very high CMRR

CMRR =		1	(	R	+	Gm	)−1
	RGm
				R		Gm
where Gm		=	I /	Vi,cm

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M11	29	7

M12	29	7

M13	22	10

M14	29	7

M15	22	6

M16	29	6

M17	29	7

M18	22	10

M19	22	6

M20	29	6

M21	20	9

M22	6	12

M23	28	6

M24	6	14

M25	20	9

M26	6	12

M27	28	6

M30	6	14

M11	29	7

M12	29	7

M13	22	10

M14	29	7

M15	22	6

M16	29	6

M17	29	7

M18	22	10

M19	22	6

M20	29	6

M21	20	9

M22	6	12

M23	28	6

M24	6	14

M25	20	9

M26	6	12

M27	28	6

M30	6	14

M11	29	7

M12	29	7

M13	22	10

M14	29	7

M15	22	6

M16	29	6

M17	29	7

M18	22	10

M19	22	6

M20	29	6

M21	20	9

M22	6	12

M23	28	6

M24	6	14

M25	20	9

M26	6	12

M27	28	6

M30	6	14