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ARM PrimeCell synchronous static memory controller technical reference manual.pdf
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Chapter 4

Programmer’s Model for Test

This chapter describes the additional logic for functional verification and production testing. It contains the following sections:

Scan testing on page 4-2

Test registers on page 4-3.

ARM DDI 0236A

Copyright © 2001. All rights reserved.

4-1

Programmer’s Model for Test

4.1Scan testing

The PrimeCell SSMC has been designed to simplify:

the insertion of scan test cells

the use of Automatic Test Pattern Generation (ATPG).

This is the recommended method of manufacturing test.

4-2

Copyright © 2001. All rights reserved.

ARM DDI 0236A