Functional Overview

Figure 2-11 External memory 32-bit burst read from 8-bit memory timing diagram

2.2.7Synchronous static memory read control

Single synchronous read operations have the same control signal timing as an asynchronous read operation, but with different timing requirements for setup and hold relative to the clock. As the output signals of the SSMC are generated internally from clocked logic, the timing for single synchronous reads is the same as for asynchronous reads.

Synchronous burst read transfers are performed differently to asynchronous burst reads, due to the internal address incrementing performed by synchronous burst devices. The SMADDR outputs are held with the initial address value, and the SMADDRVALID output is asserted during the transfer to indicate that the address is valid.

For some memory devices the signal SMBAA is used to cause the address to be advanced. This signal is only active if the BIReadEn or BIWriteEn bit is set in the bank control register, SMBCRx.

The nSMIND signal is used to indicate that the address counter (A0 to A4) has reached b11111. nSMIND=1 at all other times. nSMIND is enabled by the BIReadEn bit in the bank control register. The signal is not active during write accesses.

Four, eight, or continuous synchronous burst lengths are supported, and are controlled by the BurstLenRead bits in the bank control register SMBCRx when the SyncEnRead and BMRead bits indicate that the device supports synchronous bursts.

Figure 2-12 on page 2-20 shows a single synchronous read. WSTRD is set to 3 and

WSTBRD is set to zero.

Functional Overview

HCLK,

SMMEMCLK

HADDRSMC A

HWRITESMC

HREADYOUTSMC

SMFBCLK

SMBAA

SMADDRVALID

SMCS, nSMOEN

WSTRD=3

Figure 2-12 External synchronous single transfer read timing diagram

Figure 2-13 on page 2-21 shows a fixed-length synchronous burst of four read transfers, where WSTRD=3, and WSTBRD=0. An eight-transfer burst is performed in a similar way if HBURST indicates a burst of eight or more transfers.

Functional Overview

WSTRD=3

Figure 2-13 External synchronous fixed length four transfer burst read timing diagram

As with asynchronous bursts, AHB reads with a size greater than the external memory might generate external burst transfers. For example, a 32-bit read from an 8-bit burst device generates a four-transfer burst to the external device.

Figure 2-14 on page 2-22 shows a zero wait continuous burst, where WSTRD=3, and WSTBRD=0. Incrementing bursts of undefined length are the only AHB burst types that generate continuous external bursts.

Functional Overview