Functional Overview

2.2.13Synchronous external wait control

Burst transfers can be waited externally. This is done by using the SMBURSTWAIT signal. You must program the memory so that SMBURSTWAIT is asserted in the cycle before the delay is to apply. An example transfer where the transfer is delayed by two cycles is shown in Figure 2-29.

nSMWEN SMBURSTWAIT

Figure 2-29 Synchronous burst write with two cycle external delay (WSTWR=0 and WSTWE=0) timing diagram

Figure 2-30 on page 2-38 shows an external synchronous wait applied to a zero wait continuous burst, where the read from location A+18 is delayed by two cycles.

Functional Overview

SMBURSTWAIT

Figure 2-30 External burst wait during synchronous continuous length burst read timing diagram

The nSMBURSTWAIT signal is used by the external device to indicate that the current burst transfer is delayed, for example when crossing an address boundary. The nSMBURSTWAIT input can be synchronously asserted at any time. The latest it must be deasserted is during the cycle that the read data is valid as shown in Figure 2-30.

The signals SMWAIT and CANCESMWAIT are not used during synchronous transfers. This means there is no way to cancel the wait as for asynchronous devices.