Programmer’s Model
SSMCPeriphID1 register
The SSMCPeriphID1 register is hard-coded and the fields within the registers determine the reset value. Table 3-15 shows the bit assignment of the SSMCPeriphID1 register.
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Table 3-15 SSMCPeriphID1 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must be read as zeros |
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7:4 |
Designer0 |
These bits read back as 0x1 |
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3:0 |
PartNumber1 |
These bits read back as 0x0 |
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SSMCPeriphID2 register
The SSMCPeriphID2 register is hard-coded and the fields within the registers determine the reset value. Table 3-16 shows the bit assignment of the SSMCPeriphID2 register.
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Table 3-16 SSMCPeriphID2 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must read as zeros |
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7:4 |
Revision |
These bits read back as 0x0 |
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3:0 |
Designer1 |
These bits read back as 0x4 |
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SSMCPeriphID3 register
The SSMCPeriphID3 register is hard-coded and the fields within the registers determine the reset value. Table 3-17 shows the bit assignment of the SSMCPeriphID3 register.
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Table 3-17 SSMCPeriphID3 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must be written as zeros |
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7:0 |
Configuration |
These bits read back as 0x00 |
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3-20 |
Copyright © 2001. All rights reserved. |
ARM DDI 0236A |
Programmer’s Model
3.2.12PrimeCell identification registers, SSMCPCellID0-3
The SSMCPCellID0-3 registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. Figure 3-2 shows the bit assignment for the SSMCPCellID0-3 registers.
Actual register bit |
SMCPCellID3 |
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SMCPCellID2 |
SMCPCellID1 |
SMCPCellID0 |
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assignment |
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7 |
0 7 |
0 7 |
0 7 |
0 |
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31 |
24 23 |
16 15 |
8 7 |
0 |
Conceptual register |
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bit assignment |
SMCPCellID3 |
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SMCPCellID2 |
SMCPCellID1 |
SMCPCellID0 |
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Figure 3-2 PrimeCell identification register bit assignment
The four, 8-bit registers are described in the following subsections:
•SSMCPCellID0 register
•SSMCPCellID1 register on page 3-22
•SSMCPCellID2 register on page 3-22
•SSMCPCellID3 register on page 3-22.
SSMCPCellID0 register
The SSMCPCellID0 register is hard-coded and the fields within the registers determine the reset value. Table 3-18 shows the bit assignment of the SMCPCellID0 register.
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Table 3-18 SMCPCellID0 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must read as zeros |
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7:0 |
SSMCPCellID0 |
These bits read back as 0x0D |
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ARM DDI 0236A |
Copyright © 2001. All rights reserved. |
3-21 |
Programmer’s Model
SSMCPCellID1 register
The SSMCPCellID1 register is hard-coded and the fields within the registers determine the reset value. Table 3-19 shows the bit assignment of the SSMCPCellID1 register.
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Table 3-19 SSMCPCellID1 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must read as zeros |
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7:0 |
SSMCPCellID1 |
These bits read back as 0xF0 |
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SSMCPCellID2 register
The SSMCPCellID2 register is hard-coded and the fields within the registers determine the reset value. Table 3-20 shows the bit assignment of the SMCPCellID2 register.
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Table 3-20 SMCPCellID2 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must read as zeros |
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7:0 |
SSMCPCellID2 |
These bits read back as 0x05 |
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SSMCPCellID3 register
The SSMCPCellID3 register is hard-coded and the fields within the registers determine the reset value. Table 3-21 shows the bit assignment of the SSMCPCellID3 register.
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Table 3-21 SSMCPCellID3 register |
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Bits |
Name |
Function |
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15:8 |
- |
Reserved, read undefined, must read as zeros |
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7:0 |
SSMCPCellID3 |
These bits read back as 0xB1 |
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3-22 |
Copyright © 2001. All rights reserved. |
ARM DDI 0236A |