Chapter 3

Programmer’s Model

This chapter describes the registers of the ARM PrimeCell Synchronous Static Memory Controller (PL093) and provides details required when programming the microcontroller. It contains the following:

•About the programmer’s model on page 3-2

•PrimeCell SSMC registers on page 3-3.

Programmer’s Model

3.1About the programmer’s model

The base addresses for the PrimeCell SSMC bank configuration registers and memory banks can be configured to suit each particular system implementation. The base addresses must be configured by constant definitions in the Hardware Description Language (HDL) code for the AMBA address decoder. The base addresses are not software-programmable.

The PrimeCell SSMC registers and memory banks have fixed address offsets from the base addresses described above.