Functional Overview

2.3.2Clock feedback in SSMC

The pad interface block is shown in Figure 2-35. This registers data address and control signals. A bypass mode is supplied for using asynchronous devices. Each byte of the data bus is registered using one of the four feedback clocks.

The control signals are registered using a delayed version of SMMEMCLK.

Figure 2-35 Pad interface

The external clocks SMCLK[3:0] run continuously unless the SMClockEn bit in the control register, SSMCCR, is used to only enable the clock during accesses.

You must take care when connecting the external clocks SMCLK and FBCLK. A larger delay must be added to the external clocks SMCLK[3:0] and FBCLK[3:0] than to the other signals. If the clocks are heavily loaded by the system there might be no need for any other logic. Otherwise this can be achieved by using slow pads for the clocks and fast pads for the other signals.

Functional Overview

This allows the control, address, and data out to be changed before the clock reaches the memory device. The fed back clocks SMFBCLK[3:0] are delayed by the input pads more than the input data allowing the data to change before the rising edge of SMFBCLK latches the data.

Example of 8-bit memory device interconnection

Figure 2-36 shows 8-bit memory interconnection. Group 0, chip select 0, has four x8 memory devices providing a 32-bit databus width. Group 1 has two 8-bit memory devices providing a 16-bit databus width.

SMCLK[0] is used to clock the memory devices providing the low 8 bits of data. SMFBCLK[0] is generated from SMCLK[0] and used to register the low 8 bits of the databus for reads as it enters the SSMC.

SMFBCLK[2]

SMCLK[3]

SMDATA[31:24] 8-bit

SMCS[0] device

SMFBCLK[3]

Group 0 32-bit databus

Figure 2-36 8-bit memory device interconnection example

Functional Overview

Example of 16-bit memory device interconnection

Figure 2-37 shows 16-bit memory interconnection. Group 0, chip select 0, has two x16 memory devices providing a 32-bit databus width. Group 1 has one 16-bit memory device providing 16-bit databus width.

SMCLK[0] is used to clock the memory devices providing the low 16 bits of data.

SMFBCLK[0] and SMFBCLK[1] are generated from SMCLK[0] and SMCLK[1], and used to register the low 16 bits of the databus for reads as it enters the SSMC.

Figure 2-37 16-bit memory device interconnection example

Note

SMCLK[2] and SMCLK[3] are unused in this example. These clock signals can be used to clock further groups of memory devices to spread the load on the clocks.

Example of 32-bit memory device interconnection

Figure 2-38 on page 2-51 shows x32 memory interconnection. Group 0, chip select 0, has one x32 memory devices providing a 32-bit databus width. Group 1 has one x32 memory device providing 32-bit databus width.

SMCLK[0] is used to clock the memory devices providing the 32 bits of data.

SMFBCLK[0] and SMFBCLK[1], SMCLK[2] and SMCLK[3] are generated from

SMCLK[0] and used to register the 32 bits of the databus for reads as it enters the SSMC.