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          Файл:ARM PrimeCell synchronous static memory controller technical reference manual.pdf
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            - •ARM PrimeCell
 - •Contents
 - •List of Tables
 - •List of Figures
 - •Preface
 - •About this document
 - •Intended audience
 - •Using this manual
 - •Timing diagram conventions
 - •Further reading
 - •ARM publications
 - •Feedback
 - •Feedback on the ARM PrimeCell SSMC
 - •Feedback on this document
 - •Introduction
 - •1.1 About the ARM PrimeCell SSMC (PL093)
 - •1.1.1 Features of the PrimeCell SSMC
 - •1.1.2 Programmable parameters
 - •1.2 Supported memory devices
 - •1.2.1 Asynchronous memory devices
 - •1.2.2 Synchronous memory devices
 - •Functional Overview
 - •2.1 ARM PrimeCell SSMC overview
 - •2.1.1 SSMC core
 - •AMBA AHB interface
 - •Transfer control
 - •External bus interface
 - •Pad interface
 - •2.2 PrimeCell SSMC operation
 - •2.2.1 Clock frequency selection
 - •2.2.2 Memory bank select
 - •2.2.3 Access sequencing and memory width
 - •2.2.4 Wait state generation
 - •2.2.5 Write protection
 - •2.2.6 Asynchronous static memory read control
 - •Output enable programmable delay
 - •Asynchronous memory device accesses
 - •Asynchronous burst and page mode devices
 - •2.2.7 Synchronous static memory read control
 - •2.2.8 Asynchronous static memory write control
 - •Write enable programmable delay
 - •SRAM
 - •Flash memory
 - •2.2.9 Synchronous static memory write control
 - •2.2.10 Bus turnaround
 - •2.2.11 Synchronous memory devices bus turnaround
 - •2.2.12 Asynchronous external wait control
 - •SMWAIT assertion timing
 - •SMWAIT deassertion timing
 - •SMWAIT timing diagrams
 - •2.2.13 Synchronous external wait control
 - •2.3.1 Byte lane control
 - •Accesses to memory banks constructed from 8-bit or non byte-partitioned memory devices
 - •Accesses to memory banks constructed from 16 or 32-bit memory devices
 - •Elimination of floating bytes on the external interface
 - •Byte lane control and data bus steering for little and big-endian configurations
 - •2.3.2 Clock feedback in SSMC
 - •Example of 8-bit memory device interconnection
 - •Example of 16-bit memory device interconnection
 - •Example of 32-bit memory device interconnection
 - •2.3.3 Example of system with single output clock
 - •2.4 Slave interface connection to the AHB
 - •2.5 Memory shadowing
 - •2.5.1 Booting from ROM after reset
 - •2.5.2 External bank SMCS7 size configuration
 - •2.6 Test interface controller
 - •2.7 Using the SSMC with an EBI
 - •Programmer’s Model
 - •3.1 About the programmer’s model
 - •3.2 PrimeCell SSMC registers
 - •SMBCRx example configurations
 - •3.2.9 SSMC status register, SSMCSR
 - •3.2.10 SSMC control register, SSMCCR
 - •SSMCPeriphID0 register
 - •SSMCPeriphID1 register
 - •SSMCPeriphID2 register
 - •SSMCPeriphID3 register
 - •SSMCPCellID0 register
 - •SSMCPCellID1 register
 - •SSMCPCellID2 register
 - •SSMCPCellID3 register
 - •Programmer’s Model for Test
 - •4.1 Scan testing
 - •4.2 Test registers
 - •4.2.1 SSMC test control register, SSMCITCR
 - •4.2.2 SSMC test input register, SSMCITIP
 - •4.2.3 SSMC test output register, SSMCITOP
 - •Signal Descriptions
 - •A.1 AMBA AHB interface signals
 - •A.2 AMBA AHB slave interface signals
 - •A.3 AMBA AHB master interface signals
 - •A.4 Non-AMBA signals
 - •A.5 Input/output pad signals
 - •Index
 
Preface
This preface introduces the ARM PrimeCell Synchronous Static Memory Controller (PL093) and its reference documentation. It contains the following sections:
•About this document on page x
•Feedback on page xiii.
ARM DDI 0236A  | 
	Copyright © 2001. All rights reserved.  | 
	ix  | 
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