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Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

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Электротехника

Файл:

ARM PrimeCell synchronous static memory controller technical reference manual.pdf

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https://manualmachine.com

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23.08.2013

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Functional Overview

Elimination of floating bytes on the external interface

The PrimeCell SSMC uses the programmed external memory width of each bank and the endianness to determine which remaining bytes it must drive to ensure that the external bus is never floating.

The input/output pads cells for the external write data bus lines are controlled by nSMDATAEN[3:0] according to Table 2-4. Data is driven out on SMDATAOUTwhen nSMDATAEN is asserted LOW.

Table 2-4 SMDATAOUT controlled by nSMDATAEN

nSMDATAEN	SMDATAOUT

0	7:0

1	15:8

2	23:16

3	31:24

Byte lane control and data bus steering for little and big-endian configurations

Table 2-5 on page 2-44 to Table 2-10 on page 2-47 show how the internal databuses HRDATASMC[31:0] and HWDATASMC[31:0] map onto the external databus. The two internal databuses are shown as HDATA[31:0] in the tables.This mapping of the data is affected by:

•the external databus width

•big/little-endian operation

•size of the AHB access (word, halfword, or byte as determined by HSIZE[1:0])

•alignment within word of byte and halfword accesses, as controlled by

HADDR[1:0].

ARM DDI 0236A

2-43

Functional Overview

Table 2-5 to Table 2-10 on page 2-47 show how for all combinations of big/little-endian, bus width, HSIZE[1:0]and HADDR[1:0]. For each access it is shown which external bits on the SMDATA bus maps to the internal AHB bus HDATASMC.

Table 2-5 Little-endian read, 8-bit external bus

Access: Little-endian, 8-bit external bus External data mapping on to system data bus

SMDATA[31:0] on to HDATASMC

Internal	HSIZE	HADDR	nSMBLS
transfer	HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
transfer	[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
width	[1:0]	[1:0]	[3:0]
width

Word	10	xx	1110	7:0	-	-	-
(4 transfers)	10	xx	1110	-	7:0	-	-
	10	xx	1110	-	-	7:0	-
	10	xx	1110	-	-	-	7:0

Halfword	01	1x	1110	7:0	-	-	-
(2 transfers)	01	1x	1110	-	7:0	-	-

Halfword	01	0x	1110	-	-	7:0	-
(2 transfers)	01	0x	1110	-	-	-	7:0

Byte	00	11	1110	7:0	-	-	-

Byte	00	10	1110	-	7:0	-	-

Byte	00	01	1110	-	-	7:0	-

Byte	00	00	1110	-	-	-	7:0

2-44

ARM DDI 0236A

						Functional Overview
				Table 2-6 Little-endian read, 16-bit external bus

Access: Little-endian, 16-bit external bus				External data mapping on to system data bus
				SMDATA[31:0] on to HDATASMC

Internal	HSIZE	HADDR	nSMBLS
transfer	HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
transfer	[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
width	[1:0]	[1:0]	[3:0]
width

Word	10	xx	1100	15:8	7:0	-	-
(2 transfers)	10	xx	1100	-	-	15:8	7:0

Halfword	01	1x	1100	15:8	7:0	-	-

Halfword	01	0x	1100	-	-	15:8	7:0

Byte	00	11	1101	15:8	-	-	-

Byte	00	10	1110	-	7:0	-	-

Byte	00	01	1101	-	-	15:8	-

Byte	00	00	1110	-	-	-	7:0

				Table 2-7 Little-endian read, 32-bit external bus

Access: Little-endian, 32-bit external bus				External data mapping on to system data bus
				SMDATA[31:0] on to HDATASMC

Internal	HSIZE	HADDR	nSMBLS
transfer	HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
transfer	[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
width	[1:0]	[1:0]	[3:0]
width

Word	10	xx	0000	31:24	23:16	15:8	7:0

Halfword	01	1x	0011	31:24	23:16	15:8	7:0

Halfword	01	0x	1100	31:24	23:16	15:8	7:0
(2 transfers)

Byte	00	11	0111	31:24	23:16	15:8	7.0

ARM DDI 0236A

2-45

Functional Overview

Table 2-7 Little-endian read, 32-bit external bus (continued)

Access: Little-endian, 32-bit external bus				External data mapping on to system data bus
				SMDATA[31:0] on to HDATASMC

Internal	HSIZE	HADDR	nSMBLS
transfer	HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
transfer	[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
width	[1:0]	[1:0]	[3:0]
width

Byte	00	10	1011	31:24	23:16	15.8	7:0

Byte	00	01	1101	31:24	23:16	15:8	7:0

Byte	00	00	1110	31:24	23:16	15:8	7:0

Table 2-8 Big-endian read, 8-bit external bus

Access: Big-endian, 8-bit external bus				External data mapping on to system data bus
				SMDATA[31:0] on to HDATASMC

Internal	HSIZE	HADDR	nSMBLS
transfer	HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
transfer	[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
width	[1:0]	[1:0]	[3:0]
width

Word	10	xx	1110	-	-	-	7:0
(4 transfers)	10	xx	1110	-	-	7:0	-
	10	xx	1110	-	7:0	-	-
	10	xx	1110	7:0	-	-	-

Halfword	01	1x	1110	-	-	-	7:0
(2 transfers)	01	1x	1110	-	-	7:0	-

Halfword	01	0x	1110	-	7:0	-	-
(2 transfers)	01	0x	1110	7:0	-	-	-

Byte	00	11	1110	-	-	-	7:0

Byte	00	10	1110	-	-	7:0	-

Byte	00	01	1110	-	7:0	-	-

Byte	00	00	1110	7:0	-	-	-

2-46

ARM DDI 0236A

Functional Overview

Table 2-9 Big-endian read, 16-bit external bus

Access: Big-endian, 16-bit external bus External data mapping on to system data bus

SMDATA[31:0] on to HDATASMC

Internal		HSIZE	HADDR	nSMBLS
transfer		HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
transfer		[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
width		[1:0]	[1:0]	[3:0]
width

Word		10	xx	1100	-	-	15:8	7:0
(2 transfers)		10	xx	1100	15:8	7:0	-	-

Halfword		01	1x	1100	-	-	15:8	7:0

Halfword		01	0x	1100	15:8	7:0	-	-

Byte		00	11	1100	-	-	-	7:0

Byte		00	10	1100	-	-	15:8	-

Byte		00	01	1100	-	7:0	-	-

Byte		00	00	1100	15:8	-	-	-

					Table 2-10 Big-endian read, 32-bit external bus

	Access: Big-endian, 32-bit external bus				External data mapping on to system data bus
					SMDATA[31:0] on to HDATASMC

	Internal	HSIZE	HADDR	nSMBLS
	transfer	HSIZE	HADDR	nSMBLS	[31:24]	[23:16]	[15:8]	[7:0]
	transfer	[1:0]	[1:0]	[3:0]	[31:24]	[23:16]	[15:8]	[7:0]
	width	[1:0]	[1:0]	[3:0]
	width

	Word	10	xx	0000	31:24	23:16	15:8	7:0

	Halfword	01	1x	1100	-	-	15:8	7:0

	Halfword	01	0x	0011	31:24	23:16	-	-

	Byte	00	11	1110	-	-	-	7:0

	Byte	00	10	1101	-	-	15:8	-

	Byte	00	01	1011	-	23:16	-	-

	Byte	00	00	1101	31:24	-	-	-

ARM DDI 0236A

2-47

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