Functional Overview

Figure 2-20 External memory two zero wait writes timing diagram

Flash memory

Write timing for flash memory devices is the same as for SRAM devices. For details of burst flash devices see Synchronous static memory write control.

2.2.9Synchronous static memory write control

Figure 2-21 on page 2-29 shows an example synchronous write operation. In this example the signal SMADDRVALID provides a one cycle pulse. This behavior is enabled by setting the SyncWriteDev bit in the SMBCRx register. The AddrValidWriteEn bit must also be set for synchronous write.

The signal nSMWE is only active for 1 cycle. This is active at the start of the transfer unless it is delayed using the control bits WSWE to delay it.

Functional Overview

Figure 2-21 Synchronous two wait state write timing diagram

Synchronous burst writes are supported by the SSMC. There is no write buffer so the AHB transfer must be delayed to allow the data to be output onto the SMDATA bus. The write can be controlled in the same way as reads using the bits AddrValidWriteEn, BurstLenWrite, SyncEnWrite and BMWrite contained in the bank control register, SMCRx. An example of a burst write is shown in Figure 2-22 on page 2-30.

Functional Overview

WSTWR=2

nSMWEN

Figure 2-22 Synchronous two wait state burst write with WSTWR=2 and WSTWE=2 timing diagram

2.2.10Bus turnaround

The PrimeCell AHB SSMC can be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses. The IDCY field can be programmed for up to 15 bus turnaround wait states. This is to avoid bus contention on the external memory data bus. Bus turnaround cycles are generated between external bus transfers as follows:

•read-to-read, to different memory banks

•read-to-write, to the same memory bank

•read-to-write, to different memory banks.

Figure 2-23 on page 2-31 shows a zero wait read (WSTRD=0) followed by a zero wait write (WSTWR=0) with default turnaround between the transfers. Standard AHB wait states are added to the transfers, two for the read, and one for the write.

Functional Overview