2.1.1SSMC core

The SSMC core performs read and write accesses to external memory through the

AMBA AHB slave interface. Figure 2-2 on page 2-4 shows a block diagram of the

SSMC core.

Functional Overview

Figure 2-2 SSMC core block diagram

The four main blocks of the SSMC core are:

•AMBA AHB interface

•Transfer control on page 2-5

•External bus interface on page 2-5.

•Pad interface on page 2-5.

AMBA AHB interface

The AMBA AHB interface block provides the interface to the AMBA AHB bus. It contains all of the control and status registers for the external memory banks, and the PrimeCell and Peripheral Identification registers.

Functional Overview

The AHB control signals are sampled and passed to the transfer control block, and the control signals received are used to generate the AHB response and read data outputs.

The read/write control register values are accessed through the AHB, and their values are passed to the rest of the peripheral. The read only status register values are generated from control signals within the transfer control block.

Transfer control

The transfer control block contains two main sub-blocks:

Transfer state machine

This block is used to control the transfer currently being performed.

Delay timer and wait control

This block is used to control the operation of reads, writes, and external waits when a delay is required, and to control the externally waited transfers.

External bus interface

The external bus interface block provides the interface to the external bus. It contains the logic to generate the external control signals, and the 32-bit read/write buffer used to store the data value during transfers. It is used to:

•drive the chip selects for the memory banks

•drive the write enables for the external memory banks

•drive the output enable for the external memory banks

•drive the external databus enable

•generate read enables for read data from the external memory to the AMBA AHB interface

•control the data sequencing for memory read and writes for different sizes of AHB transfer and memory width.

Pad interface

All data, address, and control signals must be passed synchronously to and from the external synchronous static memory. This block resynchronizes all of these signals to SMMEMCLK or a delayed version of this.

Moving all of the resynchronization to a separate block enables the easiest implementation of the most appropriate clock resynchronization strategy by the user.

Functional Overview

When using asynchronous devices the synchronization logic is bypassed in the pad interface.

For more details, see Clock feedback in SSMC on page 2-48.