Functional Overview
2.1ARM PrimeCell SSMC overview
The PrimeCell SSMC is an AMBA AHB slave module that can be used to provide an interface between an AMBA AHB system bus and external (off-chip) memory devices.
The PrimeCell SSMC provides support for up to eight independently configurable memory banks simultaneously. Each memory bank is capable of supporting:
•SRAM
•ROM
•flash EPROM
•burst SRAM, ROM, and flash.
Each memory bank can be configured to use either 8, 16, or 32-bit external memory data paths. The PrimeCell SSMC can be configured to support either little-endian or big-endian operation.
The PrimeCell SSMC memory banks can be configured to support:
•nonburst read and write accesses to high-speed CMOS asynchronous static RAM
•nonburst write accesses, nonburst read accesses, and asynchronous page mode read accesses to fast-boot block flash memory
•synchronous single and burst read and write accesses to synchronous static RAM. A block diagram of the PrimeCell SSMC is shown in Figure 2-1.
|
|
PrimeCell SSMC |
|
|
Memory |
AHB slave |
|
|
Memory control signals |
|
control |
SSMC core |
|
|
|
signals |
|
interface |
|
|
|
||
|
|
|
|
|
|
|
|
Data bus |
Data bus address bus |
Pad |
Data bus |
|
|
interface |
interface |
address bus |
|
|
|
|
|||
AHB master |
Test |
|
|
|
|
interface |
|
|
|
Test |
|
interface |
|
|
|
||
controller |
|
Test control signals |
|
control |
|
|
|
|
|||
|
|
|
|
|
signals |
Figure 2-1 SSMC block diagram
The four main sub-blocks in the PrimeCell SSMC design are:
SSMC core |
Performs read and write accesses to external memory through the |
|
AMBA AHB slave interface. |
2-2 |
Copyright © 2001. All rights reserved. |
ARM DDI 0236A |