Cadence / DSD 4 / lecture13-14

CSE477 L# topic.31

Irwin&Vijay, PSU, 2001

!CLK

Me

CLK

Mp

1 → 1

Out1

1 → 0

In4

PUN

In1

In2

PDN

In5

0 → 0

In3

Out2

0 → 1

(to PDN)

!CLK

Mp

CLK

Me

to other

to other

PDN’s

PUN’s

CSE477 L# topic.32

Irwin&Vijay, PSU, 2001

!CLK

CLK

1 → x

0 → x

Sum1

!A

!B

!B

!C

1

1

1

1

1 → x

!A

1

!A

1

!B

1

!C

1

!A1

!B

!CLK

0 → xC2

1

CLK

CLK

1 → x!C1

!CLK

0 → x

B0

A

0

A0

B0

C0

A

0

A

B

B

→

C

0

0

0

0

1

x

!Sum

0

C0

CLK

!CLK

0 → x

CSE477 L# topic.33

Irwin&Vijay, PSU, 2001

1

on

off

0

Out

!Out

In1

!In1

PDN1

PDN2

In2

off

on

!In2

CSE477 L# topic.34

Irwin&Vijay, PSU, 2001

1 → 0

on

→

off

off

→ on 0 → 1

Out

!Out

In1

!In1

PDN1

PDN2

In2

off→ on

on→ off

!In2

CSE477 L# topic.35

Irwin&Vijay, PSU, 2001

B

B

!B

!B

A

!A

CSE477 L# topic.36

Irwin&Vijay, PSU, 2001

Style

# Trans

Ratioed ?

Delay

Power

Comp Static

8

no

3

1

CPL*

8

no

4

3

domino

6 + 2

no

2

2 + clk

DCVSL*

10

yes

1

4