

41
REDUCE CHARGE SHARING DEGRADATION OF Vx
WEAK PULLUP
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weak pullup pMOS |
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V |
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V |
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x |
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out |
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nMOS |
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Pushes Vx to VDD unless there |
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Logic |
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is a strong pull-down path |
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Block |
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between Vout and ground. |
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CK |
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Kenneth R. Laker, University of Pennsylvania

42
SEPERATE pMOS TRANSISTORS TO PRECHARGE INTERMEDIATE HIGH CAPACITANCE NODES
VDD |
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CK |
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Vx1 |
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Vout1 |
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nMOS |
C1 |
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Logic |
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Sub-Block |
Vx2 |
Vout2 |
inputs |
nMOS |
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C2 |
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Logic |
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Sub-Block |
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nMOS Logic Block |
EFFECTIVELY ELIMINATES ALL CHARGE SHARING PROBLEMS
DURING EVALUATION
Kenneth R. Laker, University of Pennsylvania

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VDD |
43 |
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CK
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C4 |
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P4 |
G4 |
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P3 |
C3 |
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G3 |
C2 |
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P2 |
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G2 |
C1 |
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P1 |
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G1 |
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C0 |
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C1 = G1 + P1*C0
C2 = G2 + P2*G1 + P2*P1*C0
C3 = G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*C0
C4 = G4 + P4*G3 + P4*P3*G2 + P4*P3*P2*G1 + P4*P3*P2*P1*C0
Kenneth R. Laker, University of Pennsylvania

VDD
VA
VB = 0
CK
44
Vx1 = 0 at t = 0
Vout
C1
Let C1 = C2 = 0.05 pF
Vx2 = 0 at t = 0
C2
nMOS Logic Block
WITHOUT |
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VDDC1 |
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V |
¹ V |
EVALUATION:V = |
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PRECHARGE: |
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x1 |
x 2 |
x1 |
C1 + C2 |
2 |
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PRECHARGE: Vx1 = Vx2 EVALUATION: Vx1 = VDD |
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Kenneth R. Laker, University of Pennsylvania

45
NP DOMINO LOGIC (NORA or ZIPPER CMOS)
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VDD |
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DD |
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CK |
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CK |
CK |
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nMOS |
pMOS |
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logic |
inputs logic |
inputs |
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block |
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To other |
To other |
pMOS |
nMOS |
blocks |
blocks |
VDD To other
pMOS blocks
nMOS logic block
NOTE: INVERTERS ARE NOT REQUIRED AT OUTPUTS OF STAGES
ALL inputs stable when CK = 1
CK
nMOS stages
all stages precharge all stages evaluate pMOS stagesevaluate
pre-discharge
Kenneth R. Laker, University of Pennsylvania

46
NP DOMINO LOGIC (NORA or ZIPPER CMOS) EXAMPLE
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VDD |
VDD |
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DD |
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CK |
CK |
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CK |
Kenneth R. Laker, University of Pennsylvania

47
SINGLE PHASE CLOCK PIPELINED DYNAMIC CMOS STRUCTURE
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VDD |
VDD |
VDD |
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DD |
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CK |
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CK |
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inputs |
nMOS |
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pMOS |
CK |
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logic |
inputs |
logic |
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CK |
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To Next |
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nMOS |
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N-BLOCK |
P-BLOCK |
USING TRISTATE INVERTERS BETWEEN STAGES DECOUPLES THE STAGES AND ENABLES PIPILINED OPERATION.
CK - LOW: nMOS Blocks Precharge to VDD
pMOS Blocks Evaluate by selective pullup to VDD CK-HIGH: pMOS Blocks Pre-discharge to 0V
nMOS Blocks Evaluate by selective pull down to 0V Since CK-Inverse is not used, no clock skew problem can arise. PROVIDES SIMILAR PERFROMANCE TO NORA STRUCTURE.
Kenneth R. Laker, University of Pennsylvania
48
COMMON ADVANTAGES OF DYNAMIC LOGIC STYLES
1.Smaller area than fully static gates.
2.Smaller parasitic capacitances, hence higher speed.
3.Glitch free operation if DESIGNED CARFULLY.
Kenneth R. Laker, University of Pennsylvania
SUMMARY - GUIDELINES |
49 |
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1.Full complementary static logic is best option in the majority of CMOS
circuits. Noise-immunity not sensitive to kn/kp; does not involve pre charging of nodes; dissipates no DC power; layout can be automated. Large fan-in gates lead to complex circuit structures (2N transistors); larger parasitics; slower and higher dynamic power dissipation than alternatives; no clock.
2.Pseudo-nMOS static logic finds widest utility in large fan-in NOR gates. Requires only N+1 transistors for N fan-in; smaller parasitics; faster and lower dynamic power dissipation than full COS. Noise-immunity sensitive
to kn/kp; dissipates DC power when pulled down; and not well suited for automated layout; no clock.
4. CMOS domino logic should be used for low-power, high speed applications. Requires N+k transistors for N fan-in, size advantages of psuedo-nMOS; dissipates no DC power; noise immunity not sensitive to kn/kp; use of clocks enables synchronous operation. Relies on storage on soft nodes; will require exhaustive simulation at all the process corners to insure proper operation; some of the speed advantage over static gates is diminished by the required pre-charge (pre-discharge) time.
Kenneth R. Laker, University of Pennsylvania