Cadence / DSD 4 / EE560_DynLog

31

DYNAMIC CMOS TRANSMISSION GATE LOGIC

B

F1

C

D

φ1

Kenneth R. Laker, University of Pennsylvania

32

CMOS TRANSMISSION GATE DYNAMIC SHIFT REGISTER

Kenneth R. Laker, University of Pennsylvania

33

DYNAMIC CMOS PRECHARGE - EVALUATE LOGIC

Kenneth R. Laker, University of Pennsylvania

34

VDD

Z = A.(B + C) +(D.E) when CK = 1

Z = HIGH when CK = 0

Kenneth R. Laker, University of Pennsylvania

35

2.Pull-down time is degraded due to series active switch to 0.

3.Logic output value can be degraded due to charge sharing with other gate capacitances connecte to the output.

4.Minimum clock rate determined by leakage on C.

5.Maximum clock rate determined by circuit delays.

6.Inputs can only change during the precharge phase. Inputs must be stable during evaluation; otherwise an incorrect value on an input could erroneously discharge the output node.

(single phase P-E logic gates can not be cascaded)

7.Outputs must be stored during precharge, if they are required during the next evaluate phase.

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

37

HIGH PERFORMANCE DYNAMIC CMOS CIRCUITS

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

39

weak pull-up (small kp, i.e. large L/W) pMOS transistor used maintain a precharged high if the clock were to stop. Weakened so that it does not interfere with pull-down

Kenneth R. Laker, University of Pennsylvania

40

CHARGE SHARING BETWEEN OUTPUT CAPACITANCE C1 AND

INTERMEDIATE NODE CAPACITANCE C2 DURING

1.Assume initially that all inputs are 0V and voltage across C2 is at 0V.

2.During pre-charge, i.e. CK = 0, C1 is charged to VDD.

3.If the input to N1 switches from 0 to 1 during the evaluation phase, i.e.

CK = 1, charge initially stored on C1 will be shared with C2; thus, reducing the value of Vx.

Kenneth R. Laker, University of Pennsylvania