Cadence / DSD 4 / EE560_DynLog

21

M1 -> OFF, Vout -> INCREASES

+ Vout causes Vx TO INCREASE due to Cboot and diode M3 to become reverse biased such that ID3 = 0. Then iCs + iCboot ≈ 0

Kenneth R. Laker, University of Pennsylvania

23

Vx(min) determines the required capacitance ratio, i.e.

Kenneth R. Laker, University of Pennsylvania

24

SYNCHRONOUS DYNAMIC CIRUIT TECHNIQUES

t

φ2

t

phase 1

LOGIC LEVELS DURING INACTIVE CLOCK PHASE ARE STORED ON INPUT CAPS

Kenneth R. Laker, University of Pennsylvania

25

3 - STAGE DEPLETION LOAD DYNAMIC SHIFT REGISTER

MAX CLOCK FREQUENCY IS DETERMINED BY SIGNAL PROPOGATION DELAY THROUGH ONE INVERTER STAGE

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

φ1 HIGH: Vin transfers to Cin1, 1st and 3rd stage loads are OFF.

φ2 HIGH: 1st stage load turns ON , 1st stage output achieves its valid

logic level, and Vout1 is trasfers to Cin2.

φ1 HIGH: Vout2 transfers to Cin3, next Vin transfers to Cin1(pipeline), 1st and 3rd stage loads are OFF

VOL -> kdriver/kload => RATIOED DYNAMIC LOGIC

Kenneth R. Laker, University of Pennsylvania

28

GENERAL CIRCUIT STRUCTURE OF RATIOED SYNCRONOUS

DYNAMIC LOGIC

Kenneth R. Laker, University of Pennsylvania

Cini << Couti-1 for i = 2, 3 => minimize charge sharing

φ1 HIGH: Vin transfers to Cin1, 1st and 3rd stage loads are ON, 1st stage output Vout1 achieves its valid level.

φ2 HIGH: Vout1 transfers to Cin2, 2nd stage load turns ON If Vout1 = HIGH: This level transfers to Cin2.

If Vout1 = LOW: Cout1 fully discharges to Vout1 = 0 due to HIGH level stored on Cin1.

φ1 HIGH: Vout2 transfers to Cin3, next Vin transfers to Cin1(pipeline). VOL -> 0 => RATIOLESS DYNAMIC LOGIC

Kenneth R. Laker, University of Pennsylvania