Glue logic

A simple logic circuit that is used to connect complex logic circuits together. For example, an ASIC chip may contain large functions, such as a microprocessor, memory block or communications block, which are tied together via small amounts of glue logic. At the printed circuit board (PCB) level, glue logic may be implemented with simple "jelly bean" chips ("glue chips") that contain a few gates all the way to programmable logic devices 

FPGA Start-Up Clock

Specifies the signal that will be used to clock the startup sequence at the end of the FPGA configuration process.

Select a clock option in the drop-down list.

•  CCLK

Synchronizes the startup sequence to the FPGA Configuration Clock (CCLK). CCLK is internally generated if the FPGA is set for a Master configuration mode; CCLK is an input if the FPGA is set for a Slave configuration mode. This option should be set unless the device will be configured through Boundary Scan (JTAG). Note that when generating a configuration file that will be stored on a configuration PROM, the Start-Up clock should be set for CCLK (even though the PROM itself may be programmed through JTAG).

•  User Clock

Synchronizes the startup sequence to a user-defined signal connected to the CLK pin of the STARTUP primitive, which must be instantiated in the user design. Select this option when providing a startup clock to the FPGA other than CCLK or the JTAG clock (this setup is rarely used).

•  JTAG Clock

Synchronizes to the JTAG Test Clock (TCK). This clock sequences the TAP controller which provides the control logic for JTAG. Select this option when configuring the FPGA using JTAG. Note that an FPGA that is configured from a PROM should not use this option, use CCLK instead.

A simple logic circuit that is used to connect complex logic circuits together между микропроцессором и ПЛИС.

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