Comparescan User Guide

Writing Comparescan Rules

datafile1

datafile1 filename [options]

There are two datafile commands, datafile1 and datafile2. You use a datafile command to specify an SST2 database file or another type of simulation results database file.

You use the datafile1 command to define the golden simulation results database file. This command must appear only once in a rules file, and it must appear before any comparison commands in the rules file.

If you do not specify the datafile1 command in the rules file, Comparescan uses the golden file that you specify on the Compare Options form or on the command line.

Example

datafile1 golden.trn

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datafile2

datafile2 filename [options]

There are two datafile commands, datafile1 and datafile2. You use a datafile command to specify an SST2 database file or another type of simulation results database file.

You use the datafile2 command to define the test or secondary simulation results database file. This command must appear only once in a rules file, and it must appear before any comparison commands in the rules file.

If you do not specify a datafile2 command in the rules file, Comparescan uses the test file that you specify on the Compare Options form or the command line. If you do not specify a datafile2 file anywhere, Comparescan assumes that you want to compare different signals within the golden file.

Example

datafile2 test.trn

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compare

compare name1 [name2] [options]

Use the compare command to specify an absolute comparison either of two signals or of all of the signals in two modules.

The name1 and name2 arguments are either full hierarchical signal names or module names. See “Variable and Module Naming” on page 68 and “Using Fully Qualified Hierarchical Names” on page 69 for more information on specifying signal and module names.

If name is a signal name, then the rule compares two signals.

If name is a module name, then the rule compares all of the signals in the two modules.

If you specify only one name argument, Comparescan looks for a signal or module with that same name in the datafile2 file.

If two name arguments are given, then they can be two signals or modules in two different files or in the same file. See “Variable and Module Naming in Different Files” on page 70 for more information on comparing two signals or modules.

A period (.) is a special argument that identifies all signals.

For information about compare options, see Table 6-2 on page 61, Table 6-4 on page 69, “Setting compare Command Options” on page 71, “compare Command Options” on page 72, “Using a Tolerance Window in an Absolute Comparison” on page 72, and “Comparing Signal Strengths” on page 74.

compare Command Examples

Use the following syntax to compare all of the signals in the golden and test files:

compare . [options]

Use the following syntax to compare a signal in the golden file with a signal of the same name in the test file (where name is a signal name), or to compare all of the signals in a module in the golden file with all of the signals in a module of the same name in the test file (where name is a module name):

compare name1 [options]

The following rule compares the signal top.bus from the golden file with the signal top.bus from the test file:

compare top.bus

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Writing Comparescan Rules

Use the following syntax to compare one signal with another signal of a different name (where name is a signal name), or to compare all of the signals in one module with all of the signals in another module of a different name (where name is a module name):

compare name1 name2 [options]

The following rule compares the signal top.data1 with the signal top.data2:

compare top.data1 top.data2

Variable and Module Naming

Comparisons are made between two variables: the golden variable and the test or secondary variable. The two variables may be in the same .trn file or in different .trn files. The golden and test variables that you want to compare are required arguments of a compare, clkcompare, or stability command.

You can specify variable names explicitly or you can generate them automatically.

Naming Variables Explicitly

In the examples below, sum and clk are specific signals that are being compared:

compare top.adder0.sum top.adder1.sum

compare top.clk // top.clk in second file is implied test variable

Naming Variables Implicitly: Naming Modules

You specify variables implicitly when you specify a module name instead of a variable name as an argument to a compare, clkcompare, or stability command.

If you specify a module name, Comparescan includes the module and all of its children in the comparison. In each module that it compares, Comparescan compares each of the variables, according to the settings of the hierarchy-related options, such as -internal, -boundary, and -depth. See Table 6-4 on page 69 for descriptions of the hierarchy-related options.

Specifying Hierarchical Comparisons

When you specify any name with a given rule, Comparescan searches for that name first as a variable name. If Comparescan cannot find a variable that has the name that you specify, then it searches for a module that has that name. If Comparescan cannot find a module that has the name that you specify, it reports an error, and rules file processing continues with the next rule.

Comparescan User Guide

Writing Comparescan Rules

Comparing modules is a very effective way to do comparisons without having to write many rules. It is also an easy way to generate many error messages about unimportant variables.

To avoid excess error messages, you can control module compares by using the -depth,

-internal, and -boundary options. These options are described in detail in the table below:

Table 6-4 Hierarchical Comparison Options

Using Fully Qualified Hierarchical Names

You must specify the variable or module names as fully qualified hierarchical paths from the top level in the design. For example:

compare top.adder0.sum // Correctly specifies variable sum. compare top.adder0 // Specifies all variables in module top.adder0. compare top // Specifies all variables in module top.

compare sum // INCORRECT: The variable sum will not be found. compare adder0 // INCORRECT: The module adder0 will not be found.

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Using Legal Verilog Names

You can use any legal Verilog name in a rules file. This includes escaped names, part selects, and bit selects. Concatenations, however, are not legal.

Legal names include the following:

\top.$i3\.i2

top.databus[1:0]

top.databus[7:0]

top.databus

top.databus[1]

cpu.mult.reg1

Using Verilog Escaped Names

Verilog escaped sequences are allowed wherever a module or variable name is allowed. When a name is escaped, it begins with a backslash and continues until the first white space.

An example of a Verilog escaped name is as follows:

\top.$i1$i2

The delimiting white space is not part of the module or variable name, but is required to terminate the escape. This means that when you use an escaped name, you must always end the name with more than one white space character. The first white space is part of the variable name; the second white space separates the escaped name from the next item on the command line, as shown in the following example:

//Correct. There are two spaces after top.\$i3.ib2. compare top.\$i3.ib2 -pos 10ns

//INCORRECT. There is only one space after top.\$i3.ib2. compare top.\$i3.ib2 -pos 10ns

Variable and Module Naming in Different Files

The compare, clkcompare, and stability commands take a variable number of arguments. With each one of these commands that you specify, you must specify either one or two names for use in the comparison. Generally, if there is one name, that name must exist in both the golden and test files. If there are two names, the first name must exist in the golden file, and the second name must exist in the test file.

You can specify the file that you want to use to reference a signal or module by using the n:: notation. The golden file is always file 1, and the test file is always file 2. Use 1:: to reference an object in the golden file, and use 2:: to reference an object in the test file.

Comparescan User Guide

Writing Comparescan Rules

For example, the following rule behaves in exactly the same way as the default case. The 1:: and 2:: are redundant and are therefore not needed:

compare 1::top.bus 2::top.bus

The following rule compares a signal from the test file with a signal from the golden file

(reverses the default order):

compare 2::top.bit1 1::top.bit2

The following rule compares two signals, both from the golden file:

compare 1::top.data1 1::top.data2

The following rule is equivalent to the above rule if you do not specify a test file:

datafile1 golden.trn

compare top.data1 top.data2

Setting compare Command Options

Comparescan searches for compare rule options in the following order:

1.Options that you specify with the compare command

2.Options that you specify with the datafile commands

3.Options that you specify using the Compare Options form

4.Comparescan defaults

For example, if a compare command does not have a tolerance window defined, Comparescan checks the tolerance setting for the datafile1 command. If the datafile1 command has no defined tolerance window, Comparescan checks the tolerance setting in the

Compare Options form. If there is no tolerance setting in the Compare Options form, then the program uses the default tolerance setting.

Comparescan User Guide

Writing Comparescan Rules

compare Command Options

Table 6-5 on page 72 lists options that are specific to the compare command. Table 6-4 on page 69 lists the hierarchical comparison options that are also used with the compare command.

Table 6-5 compare Command Options

Using a Tolerance Window in an Absolute Comparison

When you compare two signals using the compare command, each event on the golden signal must match an event on the test signal. Comparescan produces a miscompare error for each missing or extra event.

You can use a tolerance window to allow events to match within a specific timeframe rather than at exactly the same time. If you do not specify a tolerance window, each golden event must be matched by a test event at exactly the same time.

Comparescan considers events that occur within a tolerance window to be equal. If you specify a tolerance window, Comparescan matches the golden event with the test event that is the best match. The best match is the matching test event that occurs at the time that is closest to the time of the golden event. Comparescan measures a tolerance window relative to the golden event.

Comparescan User Guide

Writing Comparescan Rules

You can often eliminate compare errors that occur because of timing differences by using a larger tolerance window. However, changing the tolerance window does not eliminate errors that are caused by extra events or missing events.

Example compare Command with Tolerance Window

The comparison that is graphed in Figure 6-1 on page 73 uses the following rule:

compare top.s1 -neg 50ns -pos 30ns

The options -neg 50ns and -pos 30ns specify a tolerance window that starts 50 nanoseconds before the golden event and ends 30 nanoseconds after the golden event.

Comparescan measures tolerance windows relative to the golden event. To match, a test event must exist within this window.

In the comparison that is graphed in Figure 6-1 on page 73, the golden event at time 500 matches with the test event labeled C. The events labeled A and B are flagged as errors.

Figure 6-1 Comparison with Tolerance Window

Tolerance Window

Golden Event

Golden Simulation

golden.trn :: top.s1

Test Simulation

test.trn :: top.s1

A B C

Events A and B are flagged as errors.

Comparescan User Guide

Writing Comparescan Rules

Comparing Signal Strengths

Signals in simulation results can have both values (0, 1, Z, X) and strengths (strong, driving, weak).

By default, Comparescan ignores signal strengths. To compare signal strengths, use the

-checkstrength option with the compare command. Comparescan then reports an error if the strengths do not match exactly when it performs the comparison.

In Verilog designs, strengths are defined as shown in the table below.

Table 6-6 Verilog Strength Definitions

Note: Verilog signals can also have ranges of strengths. Comparescan does not support ranges of strengths.

In VHDL designs, values and strengths are defined as shown in the table below:

Table 6-7 VHDL STD_LOGIC_1164 Definitions

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Writing Comparescan Rules

Table 6-7 VHDL STD_LOGIC_1164 Definitions, continued

Using when Statements with Verilog or VHDL Expressions

Both the compare and clkcompare commands have an optional when argument. You use a when statement to describe a Verilog or VHDL expression that Comparescan uses to selectively turn off or filter certain error messages.

To parse the when statement, Comparescan turns off its usual white space parsing and parses a double-quote delimited string. Within the double quotes, a signal name with embedded spaces needs to be enclosed by back quotes, (‘). This lets you use the complete Verilog or VHDL expression language in a when statement, while keeping the parser simple. During a later phase of rule building, Comparescan parses the expression using the appropriate Verilog or VHDL parser.

Comparescan evaluates a given when expression when it finds an error. If the when expression evaluates to true, Comparescan reports the error. If the when expression evaluates to false, Comparescan does not report the error.

Note: Expressions in when statements can be any legal Verilog or VHDL expression.

Function calls, however, are not supported.

Below are two examples of the use of the when statement with Verilog—one with a compare command and one with a clkcompare command:

compare . when "!top.reset"

clkcompare top.clk top when \

"!top.reset && (top.data != 0)"

Below is an example of using the when statement with VHDL. Note that the expression must be enclosed in back quotes (‘) to properly handle the colon-style VHDL naming syntax.

compare :drinkmachine_top__il.dispense -when

"(!‘:drink_machine_top_il.reset‘)"

Comparescan User Guide

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Using Timed Verilog Expressions

Timed Verilog expressions are Verilog expressions that Comparescan evaluates at an offset time. This offset time is relative to the current evaluation time.

Below are some examples of the use of a timed Verilog expression:

compare . when "#-20(!top.reset)"

clkcompare top.clk top when "#30(!top.reset && (top.data != 0))"

compare . when "#-20(!top.reset) && #40(top.data)"