- •Contents
- •Introducing Comparescan
- •Features
- •Applications
- •Organization of this Guide
- •Getting Started
- •Starting Comparescan
- •Specifying Input Files
- •Specifying Simulation Results Databases for Comparison
- •Specifying a Comparescan Rules File
- •Specifying a Comparescan Error Database for Viewing
- •Using Automatically Generated Files
- •Using the State File
- •Using the Preferences File
- •Using X Resources
- •Understanding Comparescan Exit Status Codes
- •Comparescan Tutorial
- •Accessing the Tutorial Source Files
- •Simulation Results Databases
- •Comparescan Rules Files
- •Generating a Comparescan Error Database
- •Viewing a Comparescan Error Database
- •Viewing Errors in Hierarchical Order
- •Viewing Errors in Signalscan Waves
- •Viewing Multiple Objects in Signalscan Waves
- •Viewing Errors in Time Order
- •Exiting Comparescan
- •Giving More Information in the Rules File
- •Reviewing the demo.rules Rules File
- •Using the demo.rules Rules File
- •Viewing Clocked Miscompares in Signalscan Waves
- •Comparescan Graphical User Interface
- •Comparescan Window
- •Menu Bar
- •File Menu
- •Tools Menu
- •View Menu
- •Window Menu
- •Button Bar
- •Application Examples
- •Making Absolute Comparisons
- •Specifying the Filename of an Object
- •Comparing Two Objects from the Same File
- •Comparing Two Objects on a Condition
- •Making Clocked Comparisons
- •Using One Clock and Two Simulation Files
- •Using One Clock and One Simulation File
- •Using Two Clocks and Two Simulation Files
- •Using Two Clocks and One Simulation File
- •Performing a Clock Compare with Timing Checks
- •Checking Stability
- •Specifying Objects in the Design Hierarchy
- •Command Option Examples
- •Specifying Start and End Times for Golden and Test Files
- •Specifying Start and End Times for Comparison
- •Specifying a Time Shift
- •Specifying compare Command Tolerance Windows
- •Special Syntax Examples
- •Commenting
- •Continuing Long Lines
- •Specifying Both a Golden and a Test File
- •Specifying Filenames Using UNIX Filename Syntax
- •Writing Comparescan Rules
- •Default Comparison Rules
- •Absolute and Clocked Comparisons
- •Rules File Parsing and Execution
- •Command Syntax and Options
- •General Command Syntax
- •Command Summary
- •General Command Options
- •datafile1
- •datafile2
- •compare
- •clkdef
- •clkcompare
- •stability
- •sequencetime
- •nosequencetime
- •statemapping
- •threshold
- •report
- •savedata
- •loaddata
- •translate
- •Frequently Asked Questions
- •Comparescan Input
- •Comparescan Output
- •How do I view a comparison report that I have generated?
- •Can I print a report of my errors?
- •Can I run the tool in batch mode?
- •Graphical User Interface (GUI)
- •How do I run the program without the user interface?
- •Why can’t Comparescan allocate colors?
- •How do I change the colors in the GUI?
- •Why can’t I read the text in the GUI?
- •Comparescan Features
- •How can I compare a digital simulation with an analog simulation?
- •How do I match an X value?
- •How do I compare only the top-level signals in my design?
- •How do I compare modules at different levels in the hierarchy?
- •What if I want a different tolerance window for every signal?
- •Comparescan Error Messages
- •What does “Out of Memory” mean?
- •What does “fork failed” mean?
- •Index
Comparescan User Guide
Application Examples
Checking Stability
This section contains example code for rules that use the stability command. See “stability” on page 84 for details on the stability command and for a definition of a stability check.
The following rule performs a stability check on signal cpu.shifter.z1, using the clock that is defined in c5.
stability c5 cpu.shifter.z1
The following rule performs setup checks only.
stability top.clk top.sig1 -setup 20ns
The following rule performs hold checks only.
stability top.clk top.sig1 -hold 10ns
The following rule performs both setup and hold checks.
stability top.clk top.sig1 -setup 20ns -hold 10ns
Specifying Objects in the Design Hierarchy
The examples in this section demonstrate how to compare modules and how to specify signals in particular scopes.
The following rule compares signals at different levels in the hierarchy.
compare top.sig1 top.module1.sig1
The following rule compares modules at different levels in the hierarchy.
compare top.adder1 top.module1.adder1
The following rule compares all of the internal signals at the top hierarchical level only.
compare . -internal -depth 1
The following rule compares all of the internal signals three levels down the hierarchy.
compare . -internal -depth 3
The following rule compares all of the module ports at the top hierarchical level only.
compare . -boundary -depth 1
The following rule compares all of the module ports at the top two hierarchical levels.
compare . -boundary -depth 2
December 2000 |
51 |
Product Version 1.9 |