. . .

/* read and annotate the delays */

while (fscanf(ba_fp,"%s %d",hier_name,&num_paths) != EOF)

{

/* get handle to module instance */ mod_handle = acc_handle_object(hier_name);

. . .

/* next entry in file is number of timing checks */ fscanf(ba_fp,"%d",&num_tchecks);

/* only process if there are timing checks */ if (num_tchecks > 0)

{

/* read in and process each timing check */ for (i = 0; i < num_tchecks; i++)

{

/* read in data for one timing check */

fscanf(ba_fp,"%d %s %d %s %d %lf",&tcheck_id,sig1_str, &edge1_id,sig2_str,&edge2_id,&tcheck_incdel);

/* retrieve handle to timing check */

tcheck_handle = acc_handle_tchk(mod_handle,tcheck_id, sig1_str,edge1_id,sig2_str,edge2_id);

. . .

}

}

}

} /* ba_ppt_call() */

Annotating the Delay

Determining How and Where to Place Delays

The method that you use to place the delays into the Veritool data structure depends on two factors:

■the library cell modeling methodology

■the identifiers used in the delay back annotation file

The modeling methodology used in the construction of the Verilog HDL cell library determines where you place the delays in the Veritool data structure. This dependency results from the fact that the two methods available for describing delays in the Verilog HDL—primitive output delays and module path delays—are meant to be used separately. In general, you cannot use both constructs to describe delays within the same module. Therefore, if you describe the timing of a library cell in a lumped or distributed delay manner (using primitive output delays),

Back Annotation and Delay Calculation

Back Annotating Delays

you must place the back annotated delays on primitive outputs. If you describe the timing of a library cell with module path (pin-to-pin) delays, you must place the back annotated delays on module paths.

The identifiers provided in the delay back annotation file determine the algorithm that you use to annotate the delays. If the identifiers specify the constructs that should receive the delays, you can use the handles retrieved using these identifiers. If this is not the case (for example, when the identifiers specify interconnect nets), you will have to use the access routines to trace from the identifier to the correct delay constructs.

Note that the examples presented in this chapter assume that the delays in the delay back annotation file represent incremental (interconnect only) delays. Therefore, the example routines use acc_append_delays to add the back annotated delays to the delays in the data structure. The resultant delay is the sum of the delay that appeared in the Verilog HDL source description of the cell and the back annotated delay. If the delays in your file represent total delays, your delay back annotation C-language routines must use acc_replace_delays to replace the delays in the data structure.

Annotating to Cells with Path Delays

When the path is identified

When the delay back annotation file explicitly identifies paths and their associated delays, you can retrieve handles to the indicated paths and annotate the delays directly. Figure 3-13 on page 34 shows a C-language routine fragment that reads the example delay back annotation file shown in Figure 3-4 on page 25 and, given the design shown in Figure 3-2 on page 23 and Figure 3-3 on page 24 , adds the delays to the indicated paths. Note the call to acc_configure that configures acc_append_delays to accept two delays—a rise delay for all rising transitions and a fall delay for all falling transitions.

Figure 3-13 Annotating delays onto paths explicitly identified in the delay back annotation file

/* configure for rise and fall delays */ acc_configure(accPathDelayCount,"2");

Back Annotation and Delay Calculation

Back Annotating Delays

/* read and annotate the delays */

while (fscanf(ba_fp,"%s %d",hier_name,&num_paths) != EOF)

{

/* get handle to module instance */ mod_handle = acc_handle_object(hier_name);

. . .

/* read path IDs and delays and annotate the delays */ for (i = 0; i < num_paths; i++)

{

fscanf(ba_fp,"%s %s %lf %lf",pathin_name,pathout_name, &rise,&fall);

* get a handle to the path */

curr_path = acc_handle_modpath(mod_handle,pathin_name, pathout_name);

. . .

/* add incremental delay to path */ acc_append_delays(curr_path,rise,fall);

. . .

}

. . .

}

} /* ba_ppt_call() */

When a cell output net is identified

When the delay back annotation file identifies cell output nets—like the file shown in Figure 3-5 on page 25 —and you want to place the delays on the module path delays associated with these nets, you must first identify all such path delays. Figure 3-14 on page 35 shows a C-language routine fragment that reads the file shown in Figure 3-5 on page 25 and, given the design shown in Figure 3-2 on page 23 and Figure 3-3 on page 24 , adds the delays to the appropriate paths. In order to affect only those path delays for which the output net is a path destination, the routine loops over all path delays in the module containing the net and checks each for the correct relationship before modifying the delays. Note the call to acc_configure that configures acc_append_delays to accept a rise and a fall delay.

Figure 3-14 Annotating delays onto paths whose destination nets inside cells are identified in the delay back annotation file

acc_configure(accPathDelayCount,"2");

/* read and annotate the delays */

while (fscanf(ba_fp,"%s %lf %lf",net_name,&rise,&fall) != EOF)

{

/* get handle to the net */

net_handle = acc_handle_object(net_name);

Back Annotation and Delay Calculation

Back Annotating Delays

. . .

/* get handle to the parent module instance */ mod_handle = acc_handle_parent(net_handle);

/* find correct path delays and annotate delays */ curr_path = null;

/*loop over path delay*/

while (curr_path = acc_next_modpath(mod_handle,curr_path))

{

/* check for correct path and annotate delays */ if (acc_handle_pathout(curr_path) == net_handle)

{

/add delay to path*/ acc_append_delays(curr_path,rise,fall);

. . .

}

}

}

} /* ba_conp_call() */

When an interconnect net is identified

When the delay back annotation file identifies interconnect nets—as does the file shown in Figure 3-6 on page 26 —and you want to place the delays on all module path delays associated with this net in all of the cells with output ports that feed this net, you must first identify all such path delays. Figure 3-15 on page 36 shows a C-language routine fragment that reads this file and, given the design shown in Figure 3-2 on page 23 and Figure 3-3 on page 24 , adds the delays to the appropriate path delays. The main routine uses acc_next_driver to move inside all of the modules with output ports that feed the identified net.

Figure 3-15 Annotating delays onto paths when the cell interconnect nets connected to path destination nets are identified in the delay back annotation file

char ext_net_name[LARGE_STRING]; /* external hierarchical net name */

* read and annotate the delays */

while (fscanf(ba_fp,"%s %lf %lf",ext_net_name,&rise,&fall) != EOF)

{

/* get handle to the external net */ ext_net_handle = acc_handle_object(ext_net_name);

. . .

/* scan all modules driving this net and annotate the delays */ curr_driver = null;

while ((curr_driver = acc_next_driver(ext_net_handle, curr_driver))!= null)

Back Annotation and Delay Calculation

Back Annotating Delays

{

/* get the connecting cell output net and the parent module */ int_net_handle = acc_handle_conn(curr_driver);

mod_handle = acc_handle_parent(int_net_handle);

/* find correct path delays and annotate delays */ curr_path = null;

while (curr_path = acc_next_modpath(mod_handle,curr_path))

. . .

{

/* check for correct path and annotate delays */

if (acc_handle_pathout(curr_path) == int_net_handle)

{

/*add delay to path*/ acc_append_delays(curr_path,rise,fall);

. . .

}

}

}

}

} /* ba_inp_nowired_call() */

Modifying path pulse control values

The pulse control values associated with path delays are not affected when the path delay itself is modified. You must modify these values explicitly. You can usually accomplish this within the same code that modifies the path delay. Figure 3-16 on page 37 shows an expanded version of the C-language routine fragment shown in Figure 3-13 on page 34 that resets the path pulse control values using acc_set_pulsere so that all pulses shorter than the new (combined) delay are rejected.

Figure 3-16 Setting path pulse control values using percentages passed to acc_set_pulsere

while (fscanf(ba_fp,"%s %d",hier_name,&num_paths) != EOF)

{

/* get handle to module instance */ mod_handle = acc_handle_object(hier_name);

. . .