Back Annotation and Delay Calculation

2

Creating a Back Annotator

The Programming Language Interface (PLI) Mechanism

To create your own custom delay back annotator or delay calculator within a Veritool, use the Programming Language Interface mechanism to associate your C-language routines with a new Verilog HDL system task or function name.

This process consists of the following four steps:

1.Write one or more C-language routines that use the PLI access routines to perform the delay back annotation or delay calculation function.

2.Fill in the veriusertfs data structure in the C-language source file veriuser.c. This file is provided with the Veritool release; the data structure provides a cross-reference between the new system task or function name and your C-language routines.

3.Run vconfig (the Veritool configuration program) to create a script for your system that compiles your C-language routines and links a new Veritool executable that includes these routines (and thus the new system task or function).

4.Run the script created by vconfig to link the new Veritool executable.

When you have completed this process, you call the new system task or function from your

Verilog HDL source description. During simulation, the Veritool passes control to your C- language routines to perform delay back annotation or delay calculation. Figure 2-1 on page 14 illustrates this connection.