Back Annotation and Delay Calculation

Back Annotating Delays

Figure 3-6 Delay back annotation file with interconnect nets and their associated delays

top.m1.dm1 10 12 top.m1.dm2 10 12 top.m1.q[0] 25 27 top.m1.qb[0] 30 35 top.m1.q[1] 25 27 top.m1.qb[1] 30 35

Retrieving a Handle to the Object Associated with the Delay

The first task that you must accomplish within your delay back annotation facility is to retrieve a handle to the object associated with the indicated delay. Because you are mapping objects and delays from an external utility into the Veritool environment, the object associated with a delay in the delay back annotation file is not necessarily the object that the delay will be associated with in the Veritool. The object will, however, give you a starting point for determining where to place the delay. The following is a list of design objects that are typically identified in delay back annotation files:

■nets

■module paths

■timing checks

Retrieving a Handle to a Net

The access routine acc_handle_object takes as its input a legal Verilog HDL hierarchical name and returns a handle to the object identified by the name. Thus, if the hierarchical name of a net is provided in the delay back annotation file, you may retrieve a handle to the net simply by calling acc_handle_object with this name. Figure 3-7 on page 26 shows a C routine fragment that reads the example delay back annotation file shown in Figure 3-5 on page 25 and retrieves a handle to the net associated with the indicated delays.

Figure 3-7 Retrieving a handle to a net given the hierarchical net name

void dl_read_net_delays()

{

FILE *fdin;

char *file_name, net_name[256]; int num_args, line_num = 0;

Back Annotation and Delay Calculation

Back Annotating Delays

double rise, fall; handle net, prim, driver; bool dl_verbose = false;

/*************************************************/ /*** Initialize access routines and set version***/ /*************************************************/ acc_initialize(); acc_configure(accDevelopmentVersion,"1.5a");

. . .

/**********************************************/ /*** Read and process each line in the file ***/

/**********************************************/

while ((num_args=fscanf(fdin,"%s %lf %lf",net_name,&rise, &fall)) != EOF)

{

/********************************************************/ /*** Retrieve handle to input net, make sure it is OK ***/

/********************************************************/ net = acc_handle_object(net_name);

if ((net == null) || (acc_fetch_type(net) != accNet))

{

io_printf("Warning from $back_annotate : net %s not found\n", net_name);

continue;

}

/* process delays */

. . .

}

/* clean up access routines */ acc_close();

}

Note that the delay back annotation file does not have to contain a Verilog HDL syntax net name. It must, however, contain enough information to allow you to create the net name from the identifier provided.

Retrieving a Handle to a Module Path Delay

In order to retrieve a handle to a module path delay, the delay back annotation file must contain the following pieces of information:

■the hierarchical instance name of the module containing the path delay

■the name of the path source net

■the name of the path destination net

Given this information, you can retrieve a handle to the path delay with the access routine acc_handle_modpath. Figure 3-4 on page 25 and Figure 3-8 on page 28 show an example delay back annotation file that corresponds to the design shown in Figure 3-2 on

Back Annotation and Delay Calculation

Back Annotating Delays

page 23 and Figure 3-3 on page 24 . This file contains, among other things, Verilog HDL module instance names, names of path source nets and path destination nets that identify path delays within this module, and the rise and fall delays associated with these paths. Figure 3-9 on page 28 shows a C-language routine fragment that reads this file and retrieves handles to the indicated path delays.

Figure 3-8 Delay back annotation file identifying paths and their associated delays

top.m1 2 clk q 10 clk qb 10 3

366 d 0 clk 9 5

367 clk 13 d 0 3

Module instance name

top.m2 2

Path source net

clk q 25

Path destination net clk qb 30

3

366 d 0 clk 9 15

367 clk 13 d 0 7

top.m3 2 clk q 40 clk qb 50 3

366 d 0 clk 9 20

367 clk 13 d 0 17

Figure 3-9 Retrieving handles to path delays

Back Annotation and Delay Calculation

Back Annotating Delays

while (fscanf(ba_fp,"%s %d",hier_name,&num_paths) != EOF)

{

/* get handle to module instance */ mod_handle = acc_handle_object(hier_name);

. . .

/* read path IDs and delays and annotate the delays */ for (i = 0; i < num_paths; i++)

{

fscanf(ba_fp,"%s %s %lf %lf",pathin_name,pathout_name, &rise,&fall);

/* retrieve a handle to the path */

curr_path = acc_handle_modpath(mod_handle,pathin_name, pathout_name);

/* process delay */

. . .

}

}

} /* ba_ppt_call() */

Note that if a module path delay description contains more than one source or destination net, the net that appears first in the description must be used in the call to acc_handle_modpath. Therefore, the first net must be identified in the delay back annotation file.

Retrieving a Handle to a Timing Check

In order to retrieve a handle to a timing check, the delay back annotation file must contain the following information:

■the hierarchical name of the module instance containing the timing check

■the type of timing check

■the name of the net connected to the lower bound of the timing check

■the edge type specified for the lower bound net

■the name of the net connected to the upper bound of the timing check (if there is an upper bound)

Back Annotation and Delay Calculation

Back Annotating Delays

■the edge type specified for the upper bound net (if there is an upper bound)

Given this information, you can retrieve a handle to the timing check using acc_handle_tchk. The timing check and edge types are identified in calls to this routine by referencing constants defined in the access routine C-language include file acc_user.h.

Figure 3-10 on page 30 lists the constants.

Figure 3-10 Timing check identification constants defined in acc_user.h

Back Annotation and Delay Calculation

Back Annotating Delays

If possible, include these constants directly in the delay back annotation file, as done in the examples, instead of using string identifiers that are interpreted by your delay back annotation facility. This will allow for faster processing of the delay back annotation file.

If a timing check upper or lower bound net is active on more than one edge (as specified by the edge keyword), then the sum of the constants representing the edges must be used in the call to acc_handle_tchk.

Figure 3-4 on page 25 and Figure 3-11 on page 32 show an example delay back annotation file corresponding to the design in Figure 3-2 on page 23 and Figure 3-3 on page 24 . This

file contains Verilog HDL module instance names, a set of net names and constants that specify timing checks in the module instance, and the time limits associated with the timing checks.

Back Annotation and Delay Calculation

Back Annotating Delays

Figure 3-11 Example delay back annotation file identifying timing checks and their associated limits

Figure 3-12 on page 32 shows a C-language routine fragment that scans the example delay back annotation file shown in Figure 3-11 on page 32 and retrieves handles to the timing checks. The constant representing edge[01,x1] is obtained by summing accEdge01 and accEdgex1.

Figure 3-12 Retrieving handles to timing checks