Back Annotation and Delay Calculation

4

Calculating Delays

Integrated delay calculators based on access routines vary widely in complexity.

Implementation depends on the cell-modeling method, the target technology type, and the data needed for the calculation. Although these factors affect the calculation, the high-level algorithm is fairly constant. The following pseudocode gives this typical high-level algorithm.

Determine the scope of the delay calculation

While there are more cell modules for this calculation

{

Retrieve a handle to the next cell module

While there are more cell output ports or cell path delays

{

Retrieve a handle to the next output port or path delay

Retrieve a handle to the net associated with this output port or path delay Retrieve the cell type-specific delay calculation data for this net Retrieve the cell instance-specific loading data for this net

Calculate the delays

Back annotate the delays to the appropriate constructs in the data structure

}

}

Given this algorithm, it is clear that the main tasks associated with delay calculation are as follows:

■determining the scope of the delay calculation

■scanning the cells within this scope

■determining where to place the delay and scanning the appropriate structures within the cell

■retrieving cell type-specific and cell instance-specific delay calculation data

■calculating and annotating the delay

Examples Used in This Chapter

Integrated delay calculators typically use several different pieces of data to calculate a single set of delays. Regardless of whether this data is retrieved directly from the Veritool data structure or from an external source, each piece is usually associated with a particular object

Back Annotation and Delay Calculation

Calculating Delays

within the design. The objects with which data is most commonly associated are defined as follows:

■Path delays—Verilog-XL HDL module path delays

■Cell output nets—nets within cells that feed cell output ports

■Interconnect nets—nets external to all cells that connect one or more cell outputs with one or more cell inputs

Figure 4-1 on page 44 shows two cells described in the Verilog-XL HDL with lumped (primitive output) delay timing. Figure 4-2 on page 45 and Figure 4-3 on page 46 show the same cells described with path delay timing. Note that the object dff in these descriptions is a user-defined primitive (UDP). All of these cells contain delay calculation information described with specparams. The data items associated with these specparams are known as cell attributes. Refer to “Coding Data into Cell Descriptions (Attributes)” on page 56 for complete information on defining cell attributes and retrieving them using the access routines. Figure 4-4 on page 46 shows a simple circuit description that uses these two cells, as well as a top-level module that contains an instance of the circuit module. Note that the circuit and top-level modules are the same regardless of which cell pair is used. Finally, Figure 4-5 on page 47 and Figure 4-6 on page 47 show example capacitance back annotation files corresponding to these descriptions.

These descriptions and files are explained and used as a basis for the examples given in the remainder of this chapter. These files are not meant to define a standard Veritool delay calculation data format—there is no standard format. They are provided to help demonstrate the use of access routines in performing delay calculation.

Back Annotation and Delay Calculation

Calculating Delays

Figure 4-1 Cells described in the HDL with lumped (primitive output) delay timing and delay calculation information as specparams

// D flip-flop lumped delay timing model ‘celldefine

module dflop(q,qb,clk,d); input clk, d;

output q, qb;

dff g1(qi,clk,d); buf #102 g2(q,qi); not #156 g3(qb,qi);

// 2x1 multiplexer lumped delay timing model ‘celldefine

module mux21(y,i1,i2,sel); input i1, i2, sel;

output y;

bufif0 #56 g1(y,i1,sel); bufif1 #72 g2(y,i2,sel); specify

// specparam attributes specparam FanoutLoad$sel = 2,

FanoutLoad$y = 15,

FanoutLoad$ = 3, RiseStrength$y = 4, FallStrength$y = 3;

endspecify endmodule ‘endcelldefine

Back Annotation and Delay Calculation

Calculating Delays

Figure 4-2 D flip-flop cell described in the HDL with path delay timing and delay calculation information as specparams

Back Annotation and Delay Calculation

Calculating Delays

Figure 4-3 Multiplexer cell described in the HDL with path delay timing and delay calculation information as specparams

// 2x1 multiplexer path delay timing model ‘celldefine

module mux21(y,i1,i2,sel); input i1, i2, sel;

output y;

bufif0 g1(yi,i1,sel); bufif1 g2(yi,i2,sel); buf g3(y,yi);

specify

// specparam attributes specparam FanoutLoad$sel = 2,

FanoutLoad$y = 15,

Delay calculationdata

FanoutLoad$ = 3,

RiseStrength$ = 4,

FallStrength$ = 3;

// path delays

(sel *> y) = 72;

(i1,i2 *> y) = 56; endspecify

endmodule ‘endcelldefine

Figure 4-4 Circuit and top-level modules that contain instances of the cells described in Figure 4-1 on page 44 through Figure 4-3 on page 46

// Circuit module

module rmux221(q,qb,da,db,select,clk); input select, clk;

input [1:0] da, db; output [1:0] q, qb;

mux21 m1(dm1,da[0],db[0],select); mux21 m2(dm2,da[1],db[1],select); dflop m3(q[0],qb[0],clk,dm1); dflop m4(q[1],qb[1],clk,dm2);

endmodule

// Top level module module top;

reg clk, select; reg [1:0] da, db;

Back Annotation and Delay Calculation

Calculating Delays

wire [1:0] q, qb;

rmux221 m1(q,qb,da,db,select,clk); endmodule

Figure 4-5 Capacitance back annotation file with cell output nets and their associated capacitance values

top.m1.m1.y 3.6

top.m1.m2.y 4.2

Cell output net

top.m1.m3.q 6.2

Capacitance

top.m1.m3.qb 6.2 top.m1.m4.q 6.2 top.m1.m4.qb 6.2

Figure 4-6 Capacitance back annotation file with interconnect nets and their associated capacitance values

top.m1.dm1 3.6

top.m1.dm2 4.2

Interconnect net

top.m1.q[0] 6.2

Capacitance top.m1.qb[0] 6.2

top.m1.q[1] 6.2 top.m1.qb[1] 6.2