Back Annotation and Delay Calculation

3

Back Annotating Delays

When you create a back annotation facility based on access routines, the delay back annotation file is usually produced by an external utility. Because the external utility does the actual calculation work, the algorithm that you use within the delay back annotation facility is usually straightforward. The following pseudocode illustrates the typical delay back annotation algorithm.

While there are more entries in the delay back annotation file

{

Read the current entry

Retrieve a handle to the object associated with the delay

Place the delay on the appropriate constructs in the data structure

}

Given this algorithm, it is clear that the main tasks associated with delay back annotation are as follows:

■retrieving a handle to the object associated with the delay

■determining where to place the delay

■annotating the delay

Examples Used in This Chapter

The delay back annotation file typically contains pairs of design object identifiers and the delays associated with these objects. The types of objects identified in the file depend on several factors, including the following:

■the cell library modeling methodology used

■the constraints of the external utility that creates the file

■the Verilog HDL construct with which you associate the delay

The objects most commonly identified in delay back annotation files are defined as follows:

■path delays—Verilog HDL module path delays

Back Annotation and Delay Calculation

Back Annotating Delays

■timing checks—Verilog HDL timing checks

■cell output nets—nets within cells that feed cell output ports

■interconnect nets—nets (external to all cells) that connect one or more cell outputs with one or more cell inputs

Figure 3-1 on page 22 shows two cells described in the Verilog HDL with lumped (primitive output) delay timing. Figure 3-2 on page 23 shows the same cells described with path delay timing. Note that the object dff in these descriptions is a user-defined primitive (UDP).

Figure 3-3 on page 24 shows a simple circuit description that uses these two cells, as well as a top -level module that contains an instance of the circuit module. Note that the circuit and toplevel modules are the same no matter which cell pair is used. Finally, Figure 3-4 on page 25 through Figure 3-6 on page 26 show several example delay back annotation files corresponding to these descriptions.

These files are explained and used in the examples in the remainder of this chapter. These files are not meant to define a standard Veritool delay back annotation format — there is no standard format. They are provided to help demonstrate the use of access routines in performing delay back annotation.

Back Annotation and Delay Calculation

Back Annotating Delays

Figure 3-1 Cells described in the Verilog HDL with lumped (primitive output) delays

// D flip-flop lumped delay timing model ‘celldefine

module dflop(q,qb,clk,d); input clk, d;

output q, qb;

dff g1(qi,clk,d); buf #102 g2(q,qi);

not #156 g3(qb,qi);

Lumped (primitive endmodule output) delay

‘endcelldefine

// 2x1 multiplexer lumped delay timing model ‘celldefine

module mux21(y,i1,i2,sel); input i1, i2, sel;

output y;

bufif0 #56 g1(y,i1,sel); bufif1 #72 g2(y,i2,sel);

endmodule ‘endcelldefine

Back Annotation and Delay Calculation

Back Annotating Delays

Figure 3-2 Cells described in the Verilog HDL with path delays and timing checks

// D flip-flop lumped delay timing model ‘celldefine

module dflop(q,qb,clk,d); input clk, d;

output q, qb;

bufif0 g1(yi,i1,sel); bufif1 g2(yi,i2,sel); buf g3(y,yi);

specify

// path delays

(sel *> y) = 72;

Path Delay

(i1,i2 *> y) = 56; endspecify

endmodule ‘endcelldefine

Back Annotation and Delay Calculation

Back Annotating Delays

Figure 3-3 Circuit and top-level modules that contain instances of the cells described in Figure 3-1 on page 22 and Figure 3-2 on page 23

// Circuit module

module rmux221(q,qb,da,db,select,clk); input select, clk;

input [1:0] da, db; output [1:0] q, qb;

mux21 m1(dm1,da[0],db[0],select); mux21 m2(dm2,da[1],db[1],select); dflop m3(q[0],qb[0],clk,dm1); dflop m4(q[1],qb[1],clk,dm2);

endmodule

// Top-level module module top;

reg clk, select; reg [1:0] da, db; wire [1:0] q, qb;

rmux221 m1(q,qb,da,db,select,clk); endmodule

Back Annotation and Delay Calculation

Back Annotating Delays

Figure 3-4 Delay back annotation file with paths and timing checks and their associated delays

Figure 3-5 Delay back annotation file with cell output nets and their associated delays

top.m1.m1.y 10 12 top.m1.m2.y 10 12 top.m1.m3.q 25 27 top.m1.m3.qb 30 35 top.m1.m4.q 25 27 top.m1.m4.qb 30 35