Back Annotation and Delay Calculation
Introduction
Figure 1-2 Veritool simulation environment with an integrated delay calculation facility including optional back annotation functionality
Design database
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Verilog HDL |
Verilog HDL |
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library source |
design source |
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Data |
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files |
files |
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extraction |
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utility |
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Compilation |
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Back annotation file |
Back annotation and |
Veritool data |
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delay calculation |
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(physical |
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structure |
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parameters) |
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Simulation |
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Veritool |
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Prerequisites and Related Reading
Before reading this document, it is important that you understand several topics related to delay back annotation and delay calculation. A list of these topics is provided in Figure 1-3 on page 11 , along with references where further information can be obtained on each item. If necessary, please review the appropriate topic(s) before continuing with document.
Figure 1-3 Where to find prerequisite information
Topic |
Reference |
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Verilog simulation and hardware description |
Verilog-XL Reference Manual |
language (HDL) syntax |
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PLI—overview of access routines and how to |
PLI 1.0 User Guide and Reference |
create user-defined system tasks |
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C programming |
Any C reference manual or instructional |
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guide |
October 2000 |
11 |
Product Version 3.2 |
Back Annotation and Delay Calculation
Introduction
Topic |
Reference |
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ASIC cell-based design methodology |
Introductory literature on cell-based design, |
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ASIC cell library data books |
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October 2000 |
12 |
Product Version 3.2 |