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Back Annotation and Delay Calculation

Index

Symbols

$hold 31 $setup 31 $setuphold 31 $width 31

acc_append_delays 16, 34, 35, 86, 87 acc_append_pulsere 17, 38, 89 acc_close 15 to 16

acc_configure	15 to 16, 17, 34, 35, 59, 61,
87
acc_count 18, 66
acc_fetch_attribute 56, 57, 59, 60, 61
acc_fetch_defname 40, 56
acc_fetch_delays 16
acc_fetch_paramval 40
acc_fetch_pulsere 17, 38, 89
acc_handle_conn 81
acc_handle_modpath 27
acc_handle_object 18, 26
acc_handle_parent 49, 61, 89
acc_handle_pathout 53
acc_handle_tchk 30, 31
acc_handle_terminal 18
acc_handle_tfarg 48
acc_initialize	15 to 16

acc_next_cell 17, 51, 79, 109, 118 acc_next_cell_load 18, 61, 67 acc_next_child 17, 18 acc_next_driver 36, 38, 81 acc_next_hiconn 74, 76 acc_next_load 18, 61, 67 acc_next_loconn 54, 55, 76 acc_next_modpath 40, 52, 56 acc_next_net 18 acc_next_primitive 18 acc_next_terminal 18 acc_replace_delays 16, 34, 87 acc_replace_pulsere 17, 38, 89 acc_set_pulsere 17, 37, 88 acc_user.h 15, 30 accDevelopmentVersion 15 to 16

access routines			7
compatibility with future versions							16
effect of source protection						18
effect of timescales					17
fetch	15
handle	15
limitations		15
location in PLI Reference Manual							19
modify	15
next 15
operations on delays					16
overview		14 to 15
required routines				15 to 16
timing information				16 to 17
utility	15
annotating delays
to mixed delay libraries 40
to path delays			34 to 38
to primitive output				38 to 40
to timing checks				41
ASIC cell-based designs					8, 11
attributes	43
associating with multiple
	objects		60 to 61
coding and retrieving					56 to 61
default path delimiter string						59
defined 57
examples 44, 45, 46, 59, 61
specparam naming conventions							57

back annotation 9
capacitance file creation	10
prior to delay calculation	10

capacitance actual 63

back annotation 10 determining how to retrieve 63

due to interconnect nets 56, 63 to 84 estimation 10, 63

October 2000

143

Product Version 3.2

Back Annotation and Delay Calculation

example back annotation file 47
hash table lookup 68
nets associated with			74 to ??
retrieving from a file			68 to 74
cell output nets
defined 21, 43
identified in delay back annotation
file	25
retrieving associated interconnect
nets	74 to ??
cell output ports
retrieving handle to connected nets						54
scanning	54 to 55
cells
+nolibcell	8
‘celldefine	8
‘endcelldefine		8
attributes	43
coding and retrieving
attributes		56 to 61
definition	8
drive factors 56
identifying with access routines					17
interconnect delays			8
library directories and files				8
loading factors		56
randomly scanning cell instances						51
retrieving load information with access
routines		17
retrieving loading factors				61 to 62
scanning for delay calculation					48 to 51
scanning objects within cell
instance		52 to 56
scanning output ports			54 to 55
scanning path delays			52
scanning using capacitance
file	78 to 84

delay back annotation

annotating the delay 33 to 41 annotating to cells with lumped or

distributed delays 38 to 40, 93 annotating to cells with path

delays 34 to 38, 97 annotating to timing check limits 102 definition 9 to 10

determining how and where to place delays 33

example circuit			24
example files		25, 28, 32
example models			22, 23
examples	93
file creation		9
main tasks associated with							20
objects identified in file					20
overview	20
relationship to back annotation 9
retrieving a handle to a module path
delay		27 to 29
retrieving a handle to a net							26 to 27
retrieving a handle to a timing
check		29 to 32
retrieving a handle to object with
delay		26 to 32
typical algorithm			20
typical environment				9
typical objects identified						26
delay back annotation files						25
delay calculation
annotating to path delays						87 to 88
annotating to primitive output							89 to 92
attributes	56
avoiding duplication with wired logic 81
calculating and annotating
delays		85 to 92
capacitance due to interconnect
nets		63
data needed		56
determining the scope					48 to 50
determining where to place
delays		86 to 87
example capacitance file						47
example cell description						44, 45, 46, 58,
59
example circuit			46, 47
example overview				43
examples	105
external to Veri-tool				9
main tasks associated with							42
overview	42 to 43
pre-layout vs. post-layout						63
providing and retrieving data							56 to 84
retrieving load due to interconnect
nets		63 to 84
retrieving loading factors						61
scan methodology				50 to 51
scanning cell instances						48 to 51,
78 to 84
scanning objects within cell

October 2000

144

Product Version 3.2

Back Annotation and Delay Calculation

instance	52 to 56
typical algorithm	42
typical environment		11
delays
retrieving/modifying with access
routines	16
design object identifiers		20

edge 31
edge types
defined constants			30
examples
annotating delays to path delays						34,
35, 36, 87, 97
annotating delays to primitive
output 38, 39, 90, 93
annotating to timing check limits						41,
102
attributes 44, 45, 46, 58, 59, 61
calculating delays			85
capacitance back annotation file						47
capacitance estimate				67
configuring annotation routines for path
delays	34, 35
counting fanout		68
creating capacitance hash table						69,
105
delay back annotation				93
delay back annotation files					28, 32
delay calculation		105
determining delay calculation
scope	49, 50
determining how to retrieve
capacitance			65
estimating capacitance				67
hash table (capacitance)					71, 105
included with release				7
initializing access routine version						26
initializing access routines					26
lumped delay cells			22, 44
modifying path pulse control values							37,
88
path delay cells		23, 45, 46
randomly scanning cell instances						52
retrieving a handle to a net					26
retrieving a handle to a path delay							29
retrieving a handle to a timing check							32
retrieving attributes			59, 80, 81

retrieving capacitance from a hash table 73, 74, 78, 105

retrieving handle to interconnect

net 75, 77, 78
retrieving loading factors 62
scanning cell instances using
capacitance file	79, 80, 81, 82,
128
scanning path delays	53
storing net handles to avoid duplicate
calculations 84

handles
defined	15
retrieving for a net 26 to 28
retrieving for a path delay		27 to 29
retrieving for a timing check		29 to 32
hash tables	68 to 74
creating capacitance 70, 71
examples	105

interconnect delays 8

defined	8
interconnect nets
capacitance 56
defined	21, 43
identified in delay back annotation
file		26
load due to		63 to 84
retrieving from associated cell output
net		74 to 78

retrieving handle to 74 to ??

libraries

with mixed timing descriptions 56

nets

attaching attributes to 57 retrieving a handle 26 to 28

October 2000

145

Product Version 3.2

Back Annotation and Delay Calculation

P V

path delays	20, 43
annotating delays to		34 to 38, 87 to 88
attaching attributes to 57
identified in delay back annotation
file	25
modifying pulse control values				37,
88 to 89
retrieving a handle		27 to 29
retrieving path output net			53
scanning within a cell instance				52
PLI Reference Manual		11, 14, 19
primitive output
annotating delays to		38 to 40, 89 to 92
Programming Language Interface (PLI)
overview	13
Programming Language Interface
mechanism 7, 13
pulse control
retrieving and modifying			17, 88 to 89

vconfig	13
Verifault-XL		7
Verilog-XL		7
Verilog-XL Reference Manual 11, 18
Veritime	7
veriuser.c		13, 93

veriusertfs data structure 13, 49, 93

tf_getinstance	49
timescales 17
timing checks	21
defined constants		30 to 32
identified in delay back annotation
file	25, 32
identifying when multiple edges are
used	31
retrieving a handle		29 to 32