Back Annotation and Delay Calculation

1

Introduction

Cell interconnect delays depend on how cells are connected together within a circuit.

Therefore, these delays cannot be hard coded into the Verilog Hardware Description

Language (HDL) module descriptions that represent the cells. To incorporate these types of delays into a Verilog-XL™, Verifault-XL®, or Veritime™ (herein after referred to as the Veritools) simulation process, you must use the Programming Language Interface (PLI) access routines to create custom delay back annotators and delay calculators.

About These Application Notes

These application notes explain how you can use a particular subset of the PLI access routines to retrieve and modify Veritool data structure information for the purpose of performing delay back annotation and delay calculation. To use the PLI access routines, you must call them from within your own C-language routines, then use the Programming Language Interface (PLI) mechanism to link them with the Veritools.

Although the methods of delay-back annotation and delay calculation depend on the technology type of the design being simulated, the modeling methodology and other factors, these application notes concentrate on the problems and tasks that are most common to access-routine-based facilities.

Whenever possible, these application notes use for examples portions of the sample C- language source code supplied with the following Veritool releases:

■Verilog-XL versions 1.5a and later

■Verifault-XL versions 1.1a and later

■Veritime—available with a future version

Please note that, although the explanations and examples in these application notes are presented within the context of ASIC cell-based design and simulation, this information is applicable to other types of design methodologies.

Back Annotation and Delay Calculation

Introduction

What Is a Cell?

The lowest level building block in ASIC cell-based design is the cell. A cell is an interconnection of transistors that performs a known logical function. The timing characteristics of cells are usually known and documented, along with the logical operation of the cells, in library data books.

In the Verilog HDL, cells are typically described as modules. A cell module is usually comprised of an interconnection of primitives that perform the logical function of the cell and a set of delays that correspond to the timing characteristics of the cell.

In order to facilitate the identification of cells and the manipulation of cell definition data with the PLI access routines, the Verilog HDL provides the compiler directives ‘celldefine and

‘endcelldefine to allow you to explicitly define a module as a cell module. The access routines treat modules surrounded by these directives as cells.

Modules defined in library directories or files (using the -y or -v command line option, respectively) are treated as cell modules by the access routines unless the +nolibcell command line option is given. References to cells or cell modules within these application notes refer to modules that are defined as cells using one of these two methods. “Identifying Cells and Manipulating Cell Definition Data” on page 17 gives information on manipulating cells with access routines.

Cell Interconnect Delays

One of the most important issues that you must consider when simulating ASIC cell-based designs is the characterization of cell interconnect delays. Cell interconnect delays are the incremental delays in a system introduced when two or more cells are connected to form a circuit. In most current technologies, most cell interconnect delays are due to the capacitive effects of the following items:

■the interconnect wire used to connect cells

■the loading of cell inputs on the cell output(s) that drives them

Because cell interconnect delays depend completely on how cells connect within a circuit, the delays cannot be hard coded into the module descriptions that represent the cells. Therefore, alternate methods must be used to provide these delays: custom delay back annotators and delay calculators that you create using the PLI access routines.

Back Annotation and Delay Calculation

Introduction

What Is Delay Back Annotation?

Within the context of this document, delay back annotation is defined as a process involving the following steps:

■interpreting a set of delays for objects in a design

■placing these delays into the Veritool data structure

Design environments that use this type of process usually contain a utility (external to the

Veritool) that extracts physical information from a design database, calculates delays based on this information and outputs these delays in a form that can be accessed by the delay back annotation facility. Typically, the external utility produces a text file that contains a set of design object identifiers and the delays associated with these objects. Figure 1-1 on page 9 illustrates this type of simulation environment.

Figure 1-1 Veritool simulation environment with an integrated delay back annotation facility

Note that delay back annotation, as defined here, is a subset of the much broader back annotation, in which the data that is introduced to the simulator can be any type of information that is interpreted and used during the simulation. For example, data such as delays, wire lengths, or wire capacitance values can be introduced by back annotation. In a Veritool, the back annotation of data other than delay values must be followed by a delay calculation step in order to convert the raw numbers into delay values that are understood by the Veritool.

Therefore, the subject of non-delay back annotation (for example, back annotation of wire

Back Annotation and Delay Calculation

Introduction

capacitance values prior to delay calculation) is discussed within the context of delay calculation in these application notes.

What Is Delay Calculation?

Within the context of this document, delay calculation is defined as a process involving the following steps:

■extracting structural and cell-specific information from the Veritool data structure

■interpreting physical data provided from external sources

■using this data to calculate delays for objects within the design

■placing these delays into the Veritool data structure

Design environments that use this type of process usually contain a utility (external to the Veritool) that extracts physical parameters from a design data base and outputs these parameters in a form that can be read by the delay calculation facility.

Typically, the external utility produces a text file that contains pairs of design object identifiers and the physical parameters associated with these objects. This data provides information, such as the actual interconnect wire capacitance resulting from the layout process, that allows you to calculate very accurate delays.

You can view the interpretation of this data as a back annotation step that is incorporated within the delay calculation facility. Note that in many situations (for example, during prelayout simulations), this physical information may be estimated directly within the delay calculation facility. In these cases, the back annotation functionality is not performed. Figure 1-2 on page 11 illustrates a simulation environment that uses an integrated delay calculation facility.