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Back Annotation and Delay Calculation

Calculating Delays

Figure 4-9 Randomly scanning cell instances

static void dl_calc_prim_delays(start_mod,estimate_flag)

handle

start_mod;

bool

estimate_flag;

{

 

handle

mod, term, prim, driver;

. . .

/**********************************************************/

/*** Process

each cell module instance within the scope ***/

/**********************************************************/

mod =

null;

 

 

 

 

 

Randomly scan cell

while

(mod =

acc_next_cell(start_mod, mod))

 

 

instances

 

 

 

 

 

 

{

/* calculate delays for this cell */

. . .

}

}

Scanning Objects Within the Cell Instance

Relationship to Modeling Methodology

When a cell instance has been identified for purposes of delay calculation, you must scan the appropriate objects within the instance and calculate their associated delays. The type of object that you scan depends upon the modeling methodology used to describe timing within the target Verilog-XL HDL cell library. For cells described with path delay timing, scan the path delays within the cell instance. For cells described with lumped or distributed (primitive output) delay timing, scan the output ports of the cell instance.

Scanning Path Delays

To scan the path delays within a cell instance, use acc_next_modpath and the handle to the current instance. Figure 4-10 on page 53 shows a C-language routine fragment that uses

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Back Annotation and Delay Calculation

Calculating Delays

this method and that corresponds to the example design shown in Figure 4-2 on page 45 , Figure 4-3 on page 46 , and Figure 4-4 on page 46 . Because much of the data needed to calculate delays is associated with cell output nets, this routine uses acc_handle_pathout to retrieve the output net associated with each path.

Figure 4-10 Scanning path delays within a cell

static void dl_calc_path_delays(start_mod,estimate_flag)

handle

start_mod;

bool

estimate_flag;

{

 

handle

mod, path;

handle

pathout_net;

. . .

/**********************************************************/ /*** Process each cell module instance within the scope ***/

/**********************************************************/ mod = null;

while (mod = acc_next_cell(start_mod, mod))

{

/*********************************************/ /*** Process each path in this cell module ***/

/*********************************************/ path = null;

while (path = acc_next_modpath(mod,path))

{

Scan all path delays in cell

/*********************/

/*** Count fanouts ***/

Retrieve handle to output net

/*********************/

pathout_net = acc_handle_pathout(path);

fanout_count = acc_count(acc_next_cell_load,pathout_net);

. . .

}

. . .

}

}

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Calculating Delays

Scanning Cell Output Ports

To scan the output ports of a cell instance, use acc_next_portout with the handle to the current instance. Figure 4-11 on page 55 shows a C-language routine fragment that uses this method and that corresponds to the example design shown in Figure 4-1 on page 44 and Figure 4-4 on page 46 . Note that because much of the data needed to calculate delays is associated with cell output nets, this routine uses acc_next_loconn to retrieve the output nets associated with each port.

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Calculating Delays

Figure 4-11 Scanning cell output ports

static void dl_calc_prim_delays(start_mod,estimate_flag)

handle

start_mod;

bool

estimate_flag;

{

 

handle

mod, term, prim, driver;

handle

portout, portout_net, portout_term;

. . .

/**********************************************************/ /*** Process each cell module instance within the scope ***/

/**********************************************************/ mod = null;

while (mod = acc_next_cell(start_mod, mod))

{

/****************************************************/ /*** Process each output port in this cell module ***/

/****************************************************/ portout = null;

while (portout = acc_next_portout(mod,portout))

{

Scan cell output ports

/***********************************************/ /*** Process each net connected to this port ***/

/***********************************************/ portout_net = null;

while (portout_net = acc_next_loconn(portout,portout_net))

{

/*********************/

/*** Count fanouts ***/

Scan cell output nets connected to port

/*********************/

. . .

}

}

}

}

If all cell output and inout ports are scalars (one bit wide), then the last while loop can be replaced by a single call to acc_next_loconn because the nets connected to such ports must also be scalars.

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