Добавил:
Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
dsd1-10 / dsd-07=Verilog / backan.pdf
Скачиваний:
111
Добавлен:
05.06.2015
Размер:
697.19 Кб
Скачать

Back Annotation and Delay Calculation

Back Annotating Delays

/* read path IDs and delays and annotate the delays */ for (i = 0; i < num_paths; i++)

{

fscanf(ba_fp,"%s %s %lf %lf",pathin_name,pathout_name, &rise,&fall);

/* get a handle to the path */

curr_path = acc_handle_modpath(mod_handle,pathin_name, pathout_name);

. . .

/* add incremental delays to path */ acc_append_delays(curr_path,rise,fall);

/* set pulse control back to 100% x-generation region */ acc_set_pulsere(curr_path,0.0,1.0);

}

. . .

}

} /* ba_ppt_call() */

Use acc_append_pulsere, acc_replace_pulsere and acc_fetch_pulsere to manipulate path pulse control values in more complex ways. These routines allow you to access and modify the time values that delimit the pulse control regions directly, using actual delay values instead of percentages.

Annotating to Cells with Lumped or Distributed Delays

When a cell output net is identified

When the delay back annotation file identifies cell output nets—as does the file shown in Figure 3-5 on page 25 —and you want to place the delays on all primitives within the cell that drive this net, you can use acc_next_driver to scan all such primitives. Because acc_next_driver returns all of the primitive terminals that drive the net that is collapsed across module boundaries—and not just those within a given module—you must use caution in this situation to avoid modifying the delays on drivers in other cells. Figure 3-17 on page 38 shows a C-language routine fragment that reads this file and, given the design shown in

Figure 3-1 on page 22 and Figure 3-3 on page 24 , adds the delays to the appropriate primitives. Before modifying the delays, this routine fragment verifies that the primitive returned by acc_next_driver is in the same module as the net identified in the file.

Figure 3-17 Annotating delays to primitive outputs when a net feeding a cell output port is identified in the delay back annotation file

void dl_read_net_delays()

{

FILE *fdin;

char *file_name, net_name[256]; int num_args, line_num = 0; double rise, fall;

handle net, prim, driver, net_parent;

. . .

/**********************************************/ /*** Read and process each line in the file ***/

October 2000

38

Product Version 3.2

Back Annotation and Delay Calculation

Back Annotating Delays

/**********************************************/

while ((num_args=fscanf(fdin,"%s %lf %lf",net_name,&rise,&fall)) != EOF)

{

. . .

/****************************************************/ /*** Find handle to input net, make sure it is OK ***/

/****************************************************/ net = acc_handle_object(net_name) ;

net_parent = acc_handle_parent(net);

. . .

/***********************************************************/ /* Replace delays on all net drivers in same module as net */ /************************************************************/ driver = null;

while (driver = acc_next_driver(net,driver))

{

/*** check whether driver and net are in same module ***/

prim = acc_handle_parent(driver);

if (acc_handle_parent(prim) != net_parent) continue;

. . .

/* add delay to net driver */ acc_append_delays(driver, rise, fall);

. . .

}

}

}

Use the access routines to move farther back into the cell if more complex distribution techniques are required.

When an interconnect net is identified

When the delay back annotation file identifies cell interconnect nets—as does the file shown in Figure 3-6 on page 26 —and you want to place the delays on all of the primitives that drive the nets, you can use acc_next_driver to scan these primitives. Figure 3-18 on page 39 shows a C-language routine fragment that reads this file and, given the design shown in Figure 3-1 on page 22 and Figure 3-3 on page 24 , adds the delays to all primitive drivers.

Figure 3-18 Annotating delays to primitive outputs when an interconnect net connecting cell output ports to cell input ports is identified in the delay back annotation file

void dl_read_int_delays()

{

FILE *fdin;

char *file_name, net_name[256]; int num_args, line_num = 0; double rise, fall;

handle net, prim, driver;

. . .

/**********************************************/ /*** Read and process each line in the file ***/

/**********************************************/

October 2000

39

Product Version 3.2

Back Annotation and Delay Calculation

Back Annotating Delays

while ((num_args=fscanf(fdin,"%s %lf %lf",net_name,&rise,&fall)) != EOF)

{

. . .

/****************************************************/ /*** Find handle to input net, make sure it is OK ***/

/****************************************************/ net = acc_handle_object(net_name) ;

. . .

/*****************************************/ /*** Replace delays on all net drivers ***/

/*****************************************/ driver = null;

while (driver = acc_next_driver(net,driver))

{

. . .

/* add delay to net driver */ acc_append_delays(driver, rise, fall);

. . .

}

}

}

Use the access routines to move farther back into the cell if more complex distribution techniques are required.

Libraries with Mixed Cell Timing Descriptions

If you are annotating delays to a description containing cells with path delays and distributed delays, you must use some mechanism to determine where the delay should be placed on a cell-by-cell basis. You can accomplish this in several ways:

Delay back annotation file method —Explicitly identify the objects that should receive the delays or use some other identification mechanism directly within the delay back annotation file.

Scan method—Use acc_next_modpath to check for path delays within a cell, placing the delays on primitives if none are found.

Specparam method—Declare a specparam in all cell descriptions that indicates the type of delay methodology used within the cell and retrieve this specparam value using acc_fetch_paramval during delay back annotation.

Table lookup method—Use acc_fetch_defname to retrieve the cell type name during delay back annotation and use this name in conjunction with an external (file) or internal (data structure) table lookup mechanism to determine where the delays should be placed.

When you have determined the delay type for a particular cell instance, use the methods described previously in this section to place the delay onto the appropriate path delays or primitive drivers.

October 2000

40

Product Version 3.2

Back Annotation and Delay Calculation

Back Annotating Delays

Annotating to Timing Checks

To modify timing checks that are explicitly identified in the delay back annotation file, use the retrieved timing check handle in conjunction with the appropriate delay modification routine.

Figure 3-19 on page 41 shows a C-language routine fragment that reads the example delay back annotation file shown in Figure 3-4 on page 25 and modifies the timing check limits accordingly.

Figure 3-19 Annotating delays to timing checks

ba_ppt_call()

 

{ /* ba_ppt_call() */

 

. . .

 

int num_tchecks;

/* number of timing checks */

char sig1_str[SMALL_STRING];

/* timing check signal one string */

char sig2_str[SMALL_STRING];

/* timing check signal two string */

handle tcheck_handle;

/* handle to timing check */

int tcheck_id;

/* timing check type */

int edge1_id;

/* signal one edge type */

int edge2_id;

/* signal two edge type */

double tcheck_incdel;

/* incremental timing check limit */

. . .

 

/* read and annotate the delays */

while (fscanf(ba_fp,"%s %d",hier_name,&num_paths) != EOF)

{

/* get handle to module instance */ mod_handle = acc_handle_object(hier_name);

. . .

/* process timing checks - next entry is number of checks */ fscanf(ba_fp,"%d",&num_tchecks);

/* only process if there are timing checks */ if (num_tchecks > 0)

{

/* read in and process each timing check */ for (i = 0; i < num_tchecks; i++)

{

/* read in data for one timing check */ fscanf(ba_fp,"%d %s %d %s %d %lf",&tcheck_id,sig1_str,

&edge1_id,sig2_str,&edge2_id,&tcheck_incdel); /* get handle to timing check and add extra delay */ tcheck_handle = acc_handle_tchk(mod_handle,tcheck_id,

sig1_str,edge1_id,sig2_str,edge2_id);

. . .

/* add to timing check limit */ acc_append_delays(tcheck_handle,tcheck_incdel);

}

}

}

} /* ba_ppt_call() */

October 2000

41

Product Version 3.2

Соседние файлы в папке dsd-07=Verilog