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Национальный исследовательский университет «МИЭТ»

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Chung-Yu Wu - Analog Circuit Design

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<<< < Предыдущая 5 6 7 8 9 10 11 12 13 14 15 1617 / 4917 18 19 20 21 22 23 24 25 26 27 28 29 > Следующая >>>

8 - 6

CHUNG-YU WU

* Better input common-mode range.

* Vic↓è VDSN4↓è IDSN4↓è VA↑è MN8 is turned on è Vout→-VSS voltage spike at Vout.

*The possible spike in the settling period.

2)Improved version

+VDD

VBIAS1

M12

VBIAS2

M13

Vout

VBIAS3

M14

M10

M11

-VSS

M 12 , M13 and

M 14 : Let the drain bias currents of M 10 and M 11 follow

the change of

I D7 under positive input common mode voltage.

Þ No voltage spike at

Vout

Also serves as CMFB

* Better PSRR and input common-mode range.

C c is decoupled from the gate of the driver

M 8 .

4.Simple cascoded CMOS OP AMP

Ref.:IEEE JSSC , vol.SC-19 , pp.919~925 , Dec. 1984 +VDD

M5 M6 M8

VBIAS1	M3		M4	Vout
	M3		M4
				Cc
-	M1	M2		+
	VBIAS2	M5		M9
				M9

*Good PSRR

*Reduced input common range.

Þrestrict its applications

to those which use a virtual ground.

-VSS

5.Single-stage cascode OTA					8 - 7
5.Single-stage cascode OTA					CHUNG-YU WU
Ref.: IEEE JSSC , vol. SC-20 , pp.657~665 , June 1985
					+
			1	A	T14
	T6	T2	T4	T8	T14
				T12
	In-			T10
	In-	T1	In+	Out
		T1	T3	CL
				CL
			Io	T9
			Io
	T5			T7
	IBIAS				T17
	T11		T13	T15	T17
			T13
					-
T9 ,T10	: Cascode structure

*Output conductance ¯ without any noise penalty and with only a very small reduction of phase margin.

ÞGain- no any compensation is necessary.

*Maximum output swing¯

§8-2 Advanced Design Techniques on High-frequency Non-differential-type CMOS OP AMPs

1.Single-ended push-pull CMOS OP AMP *Current-gain-based design

M8	M9
M5
M14	M13
M15

M1	M2	M16
INPUT
	IB1
M3
	M4	M10
		M10

8 - 8

CHUNG-YU WU

+VDD

	OUTPUT
M12	CL
M12

M11

-Vcc

			TABLE I
Parameter				Measured Value

DC-Open Circuit Gain				69dB
Unity0Gain Bandwidth				70MHz
Phase Margin				40o
Slew Rate				200V / μsec
PSRR (DC+)				68dB
PSRR (DC-)				66dB
Input Offset Voltage				10mV
CMRR (DC)				62dB
Output Voltage Swing				1.5VP
Output Resistance				3 MΩ
Input Referred Noise (@1KHz)				0.54 μV / Hz
DC-Power Dissipation				1.1mWatt

VDD = +3V ;	VCC = −3V ; I B1 = 50μA		; CL=1pF
			TABLE II

Bias Current		Unity-Gain		DC-Open Circuit	DC-Power
		Bandwidth		Voltage Gain	Dissipation

25 μA		50MHz		70dB	0.55mW
50 μA		70MHz		69dB	1.1mW
100 μA		100MHz		66dB	2.2mW

VDD = +3V ; VCC = −3V ; CL=1pF 2.Low output resistance CMOS OP AMP

*C L is a compensation capacitor *For low-resistance load

*Smaller maximum output voltage swing. * I B1 = 50μA, C L = 1 pF , fu = 60MHz

8 - 9

CHUNG-YU WU

		+VDD
M8	M9
M5		M6
M5		M17
		M17
M14	M13	M22
		M18
M15		M7

				CL	OUTPUT
M1	M2			CL
M1	M2	M16		M12
INPUT				M19
	IB1			M19	M21
					M21

M3				M11
M3
	M4		M10	M20	-Vcc
			M10

§8-3 Advanced Design Techniques on High-drive MOS Power or Buffer OP AMPs

§8-3.1 Efficient Output Stages.

A. CMOS output stage using a biplar emitter follower and a low-threshold PMOS source follower.

+ VDD

VBIAS

Vout

Vin

- VSS

8 - 10

CHUNG-YU WU

B. Complementary class B output stage using compound devices with common-source output MOS.

+ VDD

Vi Vout

- VSS

§8-3.2 High-drive power or buffer CMOS OP AMPs

1.Large swing CMOS power amplifier (National Semiconductor)

					+ VDD
VIN	+	M16				M6	M9
	+
	-		A1
		-	A1	+		VOUT
				+

		C0
		M8	M8A				M10
		M8	M8A
		-	+
	VBIASN	M17	A2	M13		M12	M11
	VBIASN	M17		M13	VBIASN	M12	M11
						M6A
					-VSS

8 - 11

* Noninverting unity gain amplifier

CHUNG-YU WU

Vout

-A1

Vi ~

Vin @ Vout

+ VDD

M 6

provides the negative feedback

A1 , M 6

and

A2 , M 6 A form a class AB push-pull output stage.

Full swing from

+VDD

-VSS

M 9 , M10 , M 11, and M 12

form a current feedback to stablize the bias current

of M 6

and

M 6 A .

Offset in

,e.g.

−

-Þ V

¯Þ I

DM 6

- and

DM 9

-Þ I

DM 11

inA1

outA1

and

DM12

-Þ V

and

+ ¯

Þ V

i.e.

GSM 8A

inA2

out

+ -Þ V ¯Þ V

− ¯ (virtual

short between +

and -)

Þ V

− ¯

inA1

out

inA1

inA2

througt M 8 Þ All the bias voltage and current are restored to the normal

values and the offset is absorbed by

M 8 A .

Since the current feedback is not unity gain ,some current variation in

transistors

M 6

and

M 6 A

still exists.

VCC

M3		M4		M6
			MPC
VIN			CC	VOUT
VIN				VOUT
M1	VSS	M2
VBIASN
	M5

VSS

8 - 12

CHUNG-YU WU

Large

positive common

mode

range

allows

M 6

to source

large

amount

current to the load. (because

Vin

@ Vout )

The maximum

VGS 6

which M 1

and M 2

still in the saturation region is

VGS 6 max = −( VDD −( VIN −VGS 1 +VDSAT 1 )) = −(VCC −VIN +VTH 1 )

Þ VTH 1 -Þ VGS 6 max -Þ I DM 6 -

(1). Threshold implant to increase

VTHO1

(2). Negative substrate bias

-VSS

to increase

VTH 1

+ VCC

M3H

MP3A

VBIASP

M4H

MP4

M5A

M16

MP4A

MP3

MR C

M8A

MRF

M10

M2A

M1A

MN3A

MN4

M5A

M4A

M3A

MN5A

M17

MN3

M13

M12

M11

MN4A

M4HA

M3HA

VBIASN

- VSS

VOUT

*The input stage is not shown in the diagram.

*	M 16 , M 8 , M17 form the second				stage	with	C D the Miller compensation
	capacitor.
*	If Vout ® -VSS ,VDSM 5		® 0	and	I DSM 5	® 0.
	Þ M1 , M 2 , M 3 and M 4			are off
	Þ M 3H and	M 4H	are still on to keep VGS 6 @ 0V .
	Otherwise ,	M 6	will be turned on.
	Similarly, M 3HA and M 4HA				turn off M 6 A		in the positive voltage swing
*	M P3 , M N 3 , M N 4 , M P 4		and	M P5	are output short-circuit protection circuitry.
	Normally, M P5 is off.

88- -1314

					CHUNG-YU-YUWUWU
When	I DM 6	@ 60mA, I DMP3 -Þ I DMN 4	-Þ VGSMP5	- .
Þ I DM 6		is limited to approximately 60 mA.
		Table I
		POWER AMPLIFIER PREFORMANCE

		Parameter	Simulation		Measured
					Results

Power dissipation( ± 5V )			7.0mW		5.0mW
Avol			82dB		83dB
Fu			500KHz		420KHz
Voffset			0.4mV		1mV
PSRR+(dc)			85dB		86dB
	(1KHz)		81dB		80dB
PSRR-(dc)			104dB		106dB
	(1KHz)		98dB		98dB
THD	VIN=3.3Vp RL=300W		0.03%		0.13%(1KHz)
		CL=1000 pF	0.08%		0.32%(4KHz)
	VIN=4.0Vp RL=15 kW		0.05%		0.13%(1KHz)
		CL=200 pF	0.16%		0.20%(4KHz)
Tsettling (0.1%)			3.0us		<5.0us
Slew rate			0.8V/us		0.6V/us
1/f noise at 1KHz			N/A		130nV/Hz
Broad-band noise			N/A		49nV/Hz
Die area					1500mils2

TABLE II

COMPONENT SIZES ( μm, pF )

MI6	184/9	M8A	481/6
MI7	66/12	M13	66/12
M8	184/6	M9	27/6
M1,M2	36/10	M10	6/22
M3,M4	194/6	M11	14/6
M3H,M4H	16/12	M12	140/6
M5	145/12	MP3	8/6
M6	2647/6	MN3	244/6
MRC	48/10	MP4	43/12
CC	11.0	MN4	12/6
M1A,M2A	88/12	MP5	6/6
M3A,M4A	196/6	MN3A	6/6
M3HA,M4HA	10/12	MP3A	337/6
M5A	229/12	MN4A	24/12
M6A	2420/6	MP4A	20/12
MRF	25/12	MN5A	6/6
CF	10.0

Maximum loads : 300Ω and 1000pF to ground.

Ref.:IEEE JSSC , vol.SC-18 , pp.624-629 , Dec.1983

2. High-performance CMOS power amplifier (Siemens AG)

(1). New input stage : 3 gain stages.

		+ VDD
BIAS	M5	M10	M11
+	M1 M2	-	M13
+	M1 M2	-
		M8	M9
			CC
			M7

M3	M4	M12
		M6

- VSS

*Cc is connected to the source of M9 to improve PSRR

8 - 15

* Three poles and one zero :

CHUNG-YU WU

Z =

- 2 gm 6 g m8 g m13

LHP.

Cc g m6 g m13 + C1g m8 g m12

P @

- g ds10 g o

g m13C c

- g

+ C

)

é g

m13

æ g

+ C

) ö

2 ù1/ 2

, P @

± jê

÷ ú

ê C

where

g o

º gds12 + g ds13

CO = CL + C db12 + C db13

= C gs13 + Cdb11 + Cdb 9 + C gd 9

	Design guidelines for stability :
	g m8 large , g m13 >> g m 6
(2).	Output stage

+ VDD

VBIAS

Vout

Vin

- VSS

Class AB source follower

*One pole and one zero at high frequencies.

*Not full swing

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