64 |
Chapter 2. Architecture Overview |
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Opcode Map
The following opcode maps provide an overview of the instruction encoding for the 8051, the 80C51MX, and the 251 architecture. It is arranged as separate maps as described below:
8051 Instructions: these opcode are available on all x51 variants. Both the 2 Philips 80C51MX and the Intel/Atmel WM 251 use an OPCODE PREFIX byte
with the encoding A5 to extend the classic 8051 instruction set. The additional 251 an 80C51MX instructions are described in the following tables.
Additional 251 Instructions: if the 251 is configured in binary mode the 8051 instructions are the default opcode map and the OPCODE PREFIX is the first opcode byte for the additional 251 instructions. If the 251 is configured in source mode the additional 251 instructions are the default opcode map and the OPCODE PREFIX is the first op-code byte when the 251 should execute standard 8051 instructions that are encode with the byte values x6-xF.
Additional 80C51MX Instructions via Prefix A5: contains the 80C51MX instructions that require the OPCODE PREFIX byte. The Philips 80C51MX provides instructions for addressing the 16MB address space and the extended SFR area that are listed in this table.
Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
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8051 Instructions |
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Binary |
x0 |
x1 |
x2 |
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x3 |
x4 |
x5 |
x6-x7 |
x8-xF |
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Mode |
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Source |
x0 |
x1 |
x2 |
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x3 |
x4 |
x5 |
A5x6-A5x7 |
A5x8-A5xF |
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Mode |
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2 |
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0x |
NOP |
AJMP |
LJMP |
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RR |
INC |
INC |
INC |
INC |
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adr11 |
adr16 |
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A |
A |
dir |
@Ri |
Rn |
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1x |
JBC |
ACALL |
LCALL |
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RRC |
DEC |
DEC |
DEC |
DEC |
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bit,rel |
adr11 |
adr16 |
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A |
A |
dir |
@Ri |
Rn |
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2x |
JB |
AJMP |
RET |
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RL |
ADD |
ADD |
ADD |
ADD |
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bit,rel |
adr11 |
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A |
A,#data |
A,dir |
A,@Ri |
A,Rn |
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3x |
JNB |
ACALL |
RETI |
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RLC |
ADDC |
ADDC |
ADDC |
ADDC |
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bit,rel |
adr11 |
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A |
A,#data |
A,dir |
A,@Ri |
A,Rn |
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4x |
JC |
AJMP |
ORL |
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ORL |
ORL |
ORL |
ORL |
ORL |
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rel |
adr11 |
dir,A |
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dir,#data |
A,#data |
A,dir |
A,@Ri |
A,Rn |
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5x |
JNC |
ACALL |
ANL |
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ANL |
ANL |
ANL |
ANL |
ANL |
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rel |
adr11 |
dir,A |
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dir,#data |
A,#data |
A,dir |
A,@Ri |
A,Rn |
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6x |
JZ |
AJMP |
XRL |
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XRL |
XRL |
XRL |
XRL |
XRL |
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rel |
adr11 |
dir,A |
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dir,#data |
A,#data |
A,dir |
A,@Ri |
A,Rn |
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7x |
JNZ |
ACALL |
ORL |
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JMP |
MOV |
MOV |
MOV |
MOV |
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rel |
adr11 |
c,bit |
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@A+DPTR |
A,#data |
dir,#data |
@Ri,#data |
Rn,#data |
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8x |
SJMP |
AJMP |
ANL |
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MOVC |
DIV |
MOV |
MOV |
MOV |
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rel |
adr11 |
C,bit |
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A,@A+PC |
AB |
dir,dir |
dir,@Ri |
dir,Rn |
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9x |
MOV |
ACALL |
MOV |
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MOVC |
SUBB |
SUBB |
SUBB |
SUBB |
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DPTR,#d16 |
adr11 |
bit,c |
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A,@A+DPTR |
A,#data |
A,dir |
A,@Ri |
A,Rn |
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Ax |
ORL |
AJMP |
MOV |
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INC |
MUL |
OPCODE |
MOV |
MOV |
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C,/bit |
adr11 |
C,bit |
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DPTR |
AB |
PREFIX |
@Ri,dir |
Rn,dir |
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Bx |
ANL |
ACALL |
CPL |
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CPL |
CJNE |
CJNE |
CJNE |
CJNE |
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C,/bit |
adr11 |
bit |
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C |
A,#d8,rel |
A,dir,rel |
@Ri,#d8,rel |
Rn,#d8,rel |
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Cx |
PUSH |
AJMP |
CLR |
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CLR |
SWAP |
XCH |
XCH |
XCH |
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dir |
adr11 |
bit |
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C |
A |
A,dir |
A,@Ri |
A,Rn |
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Dx |
POP |
ACALL |
SETB |
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SETB |
DA |
DJNZ |
XCHD |
DJNZ |
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dir |
adr11 |
bit |
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C |
A |
dir,rel |
A,@Ri |
Rn,rel |
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Ex |
MOVX |
AJMP |
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MOVX |
CLR |
MOV |
MOV |
MOV |
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A,@DPTR |
adr11 |
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A,@Ri |
A |
A,dir |
A,@Ri |
A,Rn |
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Fx |
MOV |
ACALL |
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MOVX |
CPL |
MOV |
MOV |
MOV |
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@DPTR,A |
adr11 |
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@Ri,A |
A |
dir,A |
@Ri,A |
Rn,A |
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66 |
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Chapter 2. Architecture Overview |
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Additional 251 Instructions |
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Binary |
A5x8 |
A5x9 |
A5xA |
A5xB |
A5xC |
A5xD |
A5xE |
A5xF |
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Mode |
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Source |
x8 |
x9 |
xA |
xB |
xC |
xD |
xE |
xF |
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Mode |
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2 |
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0 |
JSLE |
MOV Rm |
MOVZ |
INC Rm/WRj/ |
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SRA |
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Drk,#short |
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rel |
@WRj+dis |
WRj,Rm |
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reg |
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MOV reg,ind |
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1 |
JSG |
MOV@WRj |
MOVS |
DEC Rm/WRj/ |
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SRL |
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rel |
+dis,Rm |
WRj,Rm |
Drk,#short |
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reg |
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MOV ind,reg |
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2 |
JLE |
MOV Rm, |
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ADD |
ADD |
ADD |
ADD |
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rel |
@DRk+dis |
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Rm,Rm |
WRj,WRj |
reg,op2 |
DRk,DRk |
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3 |
JG |
MOV@DRk |
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SLL |
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rel |
+dis,Rm |
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reg |
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4 |
JSL |
MOV Wrj, |
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ORL |
ORL |
ORL |
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rel |
@WRjj+dis |
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Rm,Rm |
WRj,WRj |
reg,op2 |
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5 |
JSGE |
MOV@WRj |
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ANL |
ANL |
ANL |
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rel |
+ dis,WRj |
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Rm,Rm |
WRj,WRj |
reg,op2 |
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6 |
JE |
MOV Wrj, |
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XRL |
XRL |
XRL |
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rel |
@DRk+dis |
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Rm,Rm |
WRj,WRj |
reg,op2 |
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7 |
JNE |
MOV @Drk |
MOV |
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MOV |
MOV |
MOV |
MOV |
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rel |
+dis,WRj |
op1,reg |
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Rm,Rm |
WRj,WRj |
reg,op2 |
DRk,DRk |
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8 |
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LJMP@WRj |
EJMP |
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DIV |
DIV |
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EJMP@DRk |
addr24 |
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Rm,Rm |
WRj,WRj |
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9 |
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LCALL@WR |
ECALL |
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SUB |
SUB |
SUB |
SUB |
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ECALL@DRk |
addr24 |
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Rm,Rm |
WRj,WRj |
reg,op2 |
DRk,DRk |
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A |
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BIT |
ERET |
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MUL |
MUL |
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instructions |
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Rm,Rm |
WRj,WRj |
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B |
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TRAP |
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CMP |
CMP |
CMP |
CMP |
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Rm,Rm |
WRj,WRj |
reg,op2 |
DRk,DRk |
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C |
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PUSH |
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op1 |
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D |
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POP |
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op1 |
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E |
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F |
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Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
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Additional 80C51MX Instructions via Prefix A5 |
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A5x0 |
A5x1 |
A5x2 |
A5x3 |
A5x4 |
A5x5 |
A5x6-A5x7 |
A5x8-A5xF |
A5x8-A5xF |
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0x |
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EJMP |
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INC |
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adr23 |
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esfr |
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2 |
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1x |
JBC |
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ECALL |
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DEC |
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esbit,rel |
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adr23 |
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esfr |
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2x |
JB |
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ADD |
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esbit,rel |
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A,esfr |
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3x |
JNB |
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ADDC |
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esbit,rel |
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A,esfr |
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4x |
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ORL |
ORL |
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ORL |
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EMOV |
EMOV |
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A,@PR0+d2 |
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esfr,A |
esfr,#data |
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A,esfr |
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A,@PR1+d2 |
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5x |
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ANL |
ANL |
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ANL |
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EMOV |
EMOV |
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esfr,A |
esfr,#data |
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A,esfr |
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@PR0+d2,A |
@PR1+d2,A |
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6x |
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XRL |
XRL |
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XRL |
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ADD |
ADD |
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esfr,A |
esfr,#data |
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A,esfr |
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PR0,#data2 |
PR1,#data2 |
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7x |
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ORL |
EJMP |
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MOV |
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c,esbit |
@A+EPTR |
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dir,#data |
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8x |
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ANL |
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MOV |
MOV |
MOV |
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C,esbit |
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esfr,esfr |
esfr,@Ri |
esfr,Rn |
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9x |
MOV |
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MOV |
MOVC |
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SUBB |
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EPTR,#d23 |
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esbit,c |
A,@A+EPTR |
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A,esfr |
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Ax |
ORL |
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MOV |
INC |
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MOV |
MOV |
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C,/esbit |
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C,esbit |
EPTR |
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@Ri,esfr |
Rn,esfr |
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Bx |
ANL |
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CPL |
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CJNE |
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C,/esbit |
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esbit |
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A,esfr,rel |
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Cx |
PUSH |
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CLR |
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XCH |
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esfr |
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esbit |
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A,esfr |
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Dx |
POP |
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SETB |
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DJNZ |
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esfr |
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esbit |
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esfr,rel |
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Ex |
MOVX |
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MOV |
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A,@EPTR |
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A,esfr |
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Fx |
MOV |
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MOV |
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@EPTR,A |
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esfr,A |
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68 |
Chapter 2. Architecture Overview |
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2