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Chapter 2. Architecture Overview |
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Philips 80C51MX
The Philips 80C51MX provides a unified 16 MB address space. New instructions can access up to 16MB memory whereby CODE and XDATA space are mapped into one single address space. The stack pointer can be configured as 16-Bit stack pointer that addresses the on-chip RAM area in the EDATA memory class. The following table shows the memory classes used for
2 programming the 80C51MX architecture. These memory classes are available when you are using the AX51 macro assembler and the LX51 linker/locater.
Memory Class |
Address Range |
Description |
DATA |
7F:0000 – 7F:007F |
Direct addressable on-chip RAM. |
BIT |
7F:0020 – 7F:002F |
Bit-addressable RAM; accessed bit instructions. |
IDATA |
7F:0000 – 7F:00FF |
Indirect addressable on-chip RAM; can be |
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accessed with @R0 or @R1. |
EDATA |
7F:0000 – 7F:FFFF |
Complete on-chip RAM; can be used as stack |
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space or can be accessed with @PR0 or |
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@PR1. |
XDATA |
00:0000 – 00:FFFF |
64 KB RAM (read/write access). Accessed with |
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MOVX instruction. |
HDATA |
00:0000 – 7F:FFFF |
8 MB RAM (read/write access). Accessed with |
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MOVX instruction and extended DPTR. |
CODE |
80:0000 – 80:FFFF |
Classic 8051 compatible 64 KB ROM (only read |
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access possible). Used for executable code or |
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constants. |
ECODE |
80:0000 – 80:FFFF |
8 MB ROM (only read access possible). |
HCONST |
80:0000 – 80:FFFF |
8 MB ROM. Same as ECODE, this class is |
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used by the CX51 Compiler for constants. |
BANK 0 |
80:0000 – 0xBF:FFFF |
Used by the CX51 Compiler to expand the |
… BANK 63 |
B0:0000 – B63:FFFF |
program memory to more than 64KB. Refer to |
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“Philips 80C51MX” on page 277 for more |
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information. |
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NOTES
Colons are used to improve the readability only. The addresses are entered in the tools as numbers without colon.
The memory prefixes D: I: X: C: B0: .. B31: cannot be used at Ax51 assembler level. The memory prefix is only listed for better understanding. The Lx51 linker/locater and several Debugging tools, for example the µVision2 Debugger, are using memory prefixes to identify the memory class of the address.
Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
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80C51MX Memory Layout
The Philips 80C51MX memory layout, shown in the following figure, provides a universal memory map that includes all memory types in a single 16MB address region. The memory layout of the Philips 80C51MX is shown below:
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DATA |
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2 |
FF:FFFF |
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7F:FFFF |
FF |
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SFR |
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SPACE |
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DATA |
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88 |
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ECODE |
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80 |
8MB |
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DATA |
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80 |
DA |
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TA |
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7F: |
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007F |
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EDATA |
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64KB |
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CODE |
7F:00FF |
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(= Bank 0) |
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64KB |
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80:0000 |
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7F:FFFF |
IDATA |
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EDATA |
256 Bytes |
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DATA |
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64KB |
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128 Bytes |
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7F:0000 |
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7F:0080 |
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2F |
HDATA |
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8051 |
8MB |
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Bitspace |
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DATA |
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20 |
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1F |
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00:FFFF |
128 Bytes |
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4 |
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XDATA |
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Register |
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Banks |
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64KB |
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00:0000 |
7F:0000 |
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0 |
The 80C51MX offers new CPU instructions that provide a new addressing mode, called Universal Pointer addressing. Two Universal Pointer registers PR0 and PR1 are available. PR0 is composed of registers R1, R2, and R3. PR1 is composed of registers R5, R6, and R7. These new Universal Pointer registers hold a 24-bit address that is used together with the EMOV instruction to address the complete 16MB memory.
34 Chapter 2. Architecture Overview
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Intel/Atmel WM 251 |
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Also the 251 architecture is a superset of the classic 8051 architecture. The 251 |
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is the most advanced variant and provides the following key features: |
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Completely code compatible with the standard 8051 microcontroller. |
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Powerful 8/16/32-bit instructions and flexible 8/16/32-bit registers. |
16MB linear address space and CPU support for 16-bit and 32-bit pointers. |
True stack-oriented instructions with 16-bit stack pointer.
The following table shows the memory classes used for programming a 251 microcontroller. These memory classes are available when you are using the A251 macro assembler and the L251 linker/locater.
Memory |
Address Range |
Description |
Class |
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DATA |
00:0000 - 00:007F |
Direct addressable on-chip RAM. |
BIT |
00:0020 - 00:002F |
8051 compatible bit-addressable RAM; can be accessed |
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with short 8-bit addresses. |
IDATA |
00:0000 - 00:00FF |
Indirect addressable on-chip RAM; can be accessed with |
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@R0 or @R1. |
EDATA |
00:0000 – 00:FFFF |
Extended direct addressable memory area; can be |
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accessed with direct 16-bit addresses available on the 251. |
ECONST |
00:0000 – 00:FFFF |
Same as EDATA - but allows the definition of ROM |
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constants. |
EBIT |
00:0020 - 00:007F |
Extended bit-addressable RAM; can be accessed with the |
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extended bit addressing mode available on the 251. |
XDATA |
01:0000 – 01:FFFF |
8051 compatible DATA space. Can be mapped on the 251 |
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(default space) |
to any 64 KB memory segment. Accessed with MOVX |
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instruction. |
HDATA |
00:0000 – FF:FFFF |
Full 16 MB address space of the 251. Accessed with MOV |
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@DRK instructions. This space is used for RAM areas. |
HCONST |
00:0000 – FF:FFFF |
Same as HDATA - but allows the definition of ROM |
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constants. |
ECODE |
00:0000 – FF:FFFF |
Full 16 MB address space of the 251; executable code |
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accessed with ECALL or EJMP instructions. |
CODE |
FF:0000 - FF:FFFF |
8051 compatible CODE space; used for executable code or |
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(default space) |
RAM constants. Can be located with L251 to any 64 KB |
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segment |
CONST |
FF:0000 - FF:FFFF |
Same as CODE - but can be used for ROM constants only. |
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(default space) |
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Colons are used to improve the readability only.
The addresses are entered in the tools as numbers without colon.
Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
35 |
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251 Memory Layout
The following figure shows the memory layout of the 251 architecture.
HDATA ECODE HCONST 16 MB
FF:FFFF |
00:FFFF |
DATA |
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FF |
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F8 |
2 |
CODE |
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98 |
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default page |
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FF:0000 |
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SFR |
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SPACE |
90 |
Reset Vector |
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88 |
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DATA |
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80 |
80 |
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00: |
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007F |
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EDATA |
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EBIT |
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64 KB |
00:0100 |
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251 |
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bitaddr. |
02:0000 |
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IDATA |
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XDATA |
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256 Bytes |
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DATA |
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(default, |
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128 BYTE |
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SEGMENT |
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mapable) |
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00:0080 |
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2F |
01:0000 |
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8051 |
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Bitspace |
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DATA |
20 |
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1F |
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EDATA |
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128 Bytes |
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64 KB |
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4 Register |
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Banks |
00:0000 |
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00:0000 |
0 |
The 251 completely supports all aspects of the classic 8051 memory layout and instruction set. Existing 8051 programs can be directly execute on the 251. The four 8051 memory spaces (DATA, IDATA, CODE and XDATA) are mapped into specific regions of the 16 MB address space.