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Chapter 2. Architecture Overview |
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CPU Registers
The following section provides an overview of the CPU registers that are available on the x51 variants.
In addition to the CPU registers R0 - R7, all x51 variants have an SFR space that is used to address on-chip peripherals and I/O ports. In the SFR area also reside
2 the CPU registers SP (stack pointer), PSW (program status word), A (accumulator, accessed via the SFR space as ACC), B, DPL and DPH (16-bit register DPTR).
CPU Registers of the 8051 Variants
The classic 8051 provides 4 register banks of 8 registers each. These register banks are mapped into the DATA memory area at address 0 – 0x1F. In addition the CPU provides a 8-bit A (accumulator) and B register and a 16-bit DPTR (data pointer) for addressing XDATA and CODE memory. These registers are also mapped into the SFR space as special function registers.
8 Bytes
Registerbank 3
D:0x18
Registerbank 2
D:0x10
Registerbank 1
D:0x08
Registerbank 0
D:0x00
DATA MEMORY
Some CPU variants provide extended DPTR and/or SP registers. Also several devices have multiple DPTR registers.
The active Registerbank is selected via the bits RB0 and RB1 in the program status word (PSW).
Universal Pointers on Philips 80C51MX
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PR0 |
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PR1 |
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R0 |
R1 |
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R2 |
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R3 |
R4 |
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R5 |
R6 |
R7 |
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DPTR |
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CPU REGISTER |
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DPX |
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DPH |
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DPL |
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A |
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B |
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PSW |
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SPX |
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SP |
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Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
37 |
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CPU Registers of the Intel/Atmel WM 251
The 251 architecture supports an extra 32 bytes of registers in addition to the 4 |
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banks of 8 registers found in the classic 8051. The lower 8 byte registers are |
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mapped between locations 00:00 - 00:0x1F. The lower 8 byte registers are |
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mapped in this way to support 8051 microcontroller register banking. The |
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register file can be addressed in the following ways: |
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Register 0 - 15 can be used as either byte, word, or double word (Dword) |
registers.
Register 16 - 31 can be addressed as either word or Dword registers.
Register DR56 and DR60 can be addressed only as Dword registers.
There are 16 possible byte registers (R0 - R15), 16 possible word registers (WR0 - WR30) and 10 possible Dword registers (DR0 - DR28, DR56 - DR60) that can be addressed in any combination.
All Dword registers are Dword aligned; each is addressed as DRk with “k” being the lowest of the 4 consecutive registers. For example, DR4 consists of registers 4 - 7.
All word registers are word aligned; each is addressed as WRj with “j” being the lower of the 2 consecutive registers. For example WR4 consists of registers 4 - 5.
All byte registers are inherently byte aligned; each is addressed as Rm with “m” being the register number. For example R4 consists of register 4.
38 |
Chapter 2. Architecture Overview |
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The following figure shows the register file format for the 251 microcontroller.
8 Bytes
Register 56 - 63
2
Register 8 - 31
Register 0 - 7
MEMORY
The 8051 CPU Registers A, B, DPL, DPH and SP are mapped into the 251 register file. The following 251 CPU registers are identical with the 8051 CPU registers:
8051 Register |
251 Register |
A (ACC) |
R11 |
B |
R10 |
DPL |
low byte of DR56 |
DPH |
2nd byte of DR56 |
SP |
low byte of DR60 |
The stack pointer register (DR60) of the 251 CPU is a 16-bit register. DR60 is used for all stack operations (PUSH, POP, CALL, RET, ect.) and can be also used for indirect addressing. Therefore the 251 provides efficient stack addressing modes for reentrant functions.
WR24 |
WR26 |
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WR28 |
WR30 |
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WR16 |
WR18 |
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WR20 |
WR22 |
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WR8 |
WR10 |
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WR12 |
WR14 |
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WR0 |
WR2 |
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WR4 |
WR6 |
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WORD REGISTER |
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R8 |
R9 |
R10 |
R11 |
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R12 |
R13 |
R14 |
R15 |
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R0 |
R1 |
R2 |
R3 |
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R4 |
R5 |
R6 |
R7 |
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BYTE REGISTER |
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Stack Pointer (SPX) |
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DR56 |
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DR60 |
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DR24 |
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DR28 |
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DR16 |
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DR20 |
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DR8 |
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DR12 |
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DR0 |
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DR4 |
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DWORD REGISTER |
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Stack Pointer (SPX) |
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DR56 |
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DR60 |
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DR24 |
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WR28 |
WR30 |
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WR16 |
WR18 |
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DR20 |
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WR8 |
WR10 |
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R12 |
R13 |
R14 |
R15 |
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WR0 |
R2 |
R3 |
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DR4 |
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EXAMPLE OF MIXED USAGE
Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
39 |
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Program Status Word (PSW)
The Program Status Word (PSW) contains status bits that reflect the current CPU state. The 8051 variants provide one special function register called PSW with this status information. The 251 provides two additional status flags, Z and N, that are available in a second special function register called PSW1.
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PSW Register (all 8051 and 251 variants) |
2 |
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Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
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CY |
AC |
F0 |
RS1 |
RS0 |
OV |
UD |
P |
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Additional PSW1 Register (on Intel/Atmel WM 251 only)
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
CY |
AC |
N |
RS1 |
RS0 |
OV |
Z |
– |
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The following table describes the status bits in the PSW.
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Symbol |
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Function |
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CY |
Carry flag |
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AC |
Auxiliary Carry flag (For BCD Operations) |
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F0 |
Flag 0 (Available to the user for General Purpose) |
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RS1, |
Register bank select: RS1 |
RS0 |
Working Register Bank and Address |
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RS0 |
0 |
0 |
Bank0 |
(D:0x00 - D:0x07) |
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0 |
1 |
Bank1 |
(D:0x08 - D:0x0F) |
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1 |
0 |
Bank2 |
(D:0x10 - D:0x17) |
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1 |
1 |
Bank3 |
(D:0x18H - D:0x1F) |
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OV |
Overflow flag |
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UD |
User definable flag |
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P |
Parity flag |
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251 ONLY |
– |
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Reserved for future use |
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Z |
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Zero flag |
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N |
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Negative flag |
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