Chapter 2. Architecture Overview

This chapter gives you an overview of the 8051 architecture and the variants of the 8051. It reviews the memory layout of the classic 8051, extended 8051 variants, the Philips 80C51MX, and the 251 architecture. Also described are the register sets and the CPU instructions of the various CPU variants.

2

Memory Classes and Memory Layout

This section introduces the different memory classes (also known as memory types) that are used during programming of the 8051 and variants. Memory classes are used to identify the different physical memory regions of the microcontroller architecture that can be represented in a memory layout.

An overview of the different physical memory regions in an x51 system is provided below:

Program Memory: in the classic 8051 this is a 64KB space that is called CODE. This region is typically a ROM space that is used for program code and constants. With the BL51 you may expand the physical program code memory to 32 code banks with 64KB each. Constants are fetched with the MOVC instruction. In extended 8051 variants and the 251 you may have program memory of up to 16MB that is called ECODE and HCONST.

Internal Data Memory: in the classic 8051 this is the on-chip RAM space with a maximum of 256 Bytes that contains register banks, BIT space, direct addressable DATA space, and indirect addressable IDATA space. This region should be used for frequently used variables. In the 80C51MX and the 251 this space is expanded to up to 64KB with an EDATA space.

External Data Memory: in classic 8051 devices this area, called XDATA, is off-chip RAM with a space of up to 64KB. However several new 8051 devices have additional on-chip RAM that is mapped into the XDATA space. Usually you need to enable this additional on-chip RAM via dedicated SFR registers. In extended variants and the 251 you may have external data memory of up to 16MB that is called HDATA.

Classic 8051

The following table shows the memory classes used for programming the classic 8051 architecture. These memory classes are available when you are using the A51 macro assembler and the BL51 linker/locater.

NOTE

The memory prefix D: I: X: C: B0: .. B31: cannot be used at Ax51 assembler or BL51 linker/locater level. The memory prefixes are only listed for better understanding. Several Debugging tools, for example the µVision2 Debugger, are using memory prefixes to identify the memory class of the address.

Classic 8051 Memory Layout

The classic 8051 memory layout, shown in the following figure, is familiar to 8051 users the world over.

DATA FF

F8

2

The memory code banks overlap the CODE space. The size of the code banks is selected with the Lx51 directive BANKAREA.

Extended 8051 Variants

Several new variants of the 8051 extend the code and/or xdata space of the classic 8051 with address extension registers. The following table shows the memory classes used for programming the extended 8051 devices. These memory classes are available for classic 8051 devices when you are using memory banking with the LX51 linker/locater. In addition to the code banking

2 known from the BL51 linker/locater, the LX51 linker/locator supports also data banking for xdata and code areas with standard 8051 devices.

NOTES

The memory prefixes D: I: X: C: B0: .. B31: cannot be used at Ax51 assembler level. The memory prefix is only listed for better understanding. The Lx51 linker/locater and several Debugging tools, for example the µVision2 Debugger, are using memory prefixes to identify the memory class of the address.

If you are using the Dallas 390 contiguous mode the address space for CODE can be C:0000 - C:0xFFFFFF.

Extended 8051 Memory Layout

The extended 8051 memory layout, shown in the following figure, expands the address space for variables to a maximum of 16MB.

In several variants the DPTR register is expanded to a 24-bit register with an DPX SFR. Fox example, the Dallas 390 and provides new operating modes where this addressing is enabled. You may even use the HCONST and HDATA memory classes with classic 8051 devices by using the memory banking available in LX51.