40

Chapter 2. Architecture Overview

Identifier

Explanation

2

A

Accumulator

AB

Register Pair A & B

B

Multiplication Register

C

Carry Flag

DPTR

Data pointer

PC

Program Counter

Rn

Register R0 - R7 of the currently selected Register Bank.

dir8

8-bit data address; Data RAM (D:0x00 - D:0x7F) or SFR (D:0x80 - D:0xFF)

#data8

8-bit constant included in instruction.

#data16

16-bit constant included in instruction.

addr16

16-bit destination address.

addr11

11-bit destination address. Used by ACALL & AJMP. The branch will be within the

same 2KByte block of program memory of the first byte of the following instruction.

rel

Signed (two’s complement) 8-bit offset. Used by SJMP and conditional jumps.

Range is -128 .. +127 bytes relative to the first byte of the following instruction.

bit8

Direct addressed bit in Data RAM Location.

Rm

Register R0 - R15 of the currently selected Register File.

WRj

Register WR0 - WR30 of the currently selected Register File.

DRk

Register DR0 - DR28, DR56, DR60 of the currently selected Register File.

dir16

16-bit data address; Data RAM location (00:00 - 00:FFFF).

ONLY

@WRj

Data RAM location (0 - 64K) addressed indirectly via WR0 - WR30.

251

@DRk

Data RAM location (0 - 16M) addressed indirectly via DR0 - DR28, DR56, DR60.

#short

constant 1, 2 or 4 included in instruction.

bit11

Direct addressed bit in Data RAM or Special Function Register.

@Wrj+dis

Data RAM location (0 - 64K) addressed indirectly via WR0 - WR30 + displacement.

@DRk+dis

Data RAM location (0 - 16M) addressed indirectly via DR0 - DR28, DR56, DR60+

16-bit signed displacement.

EPTR

23-bit extended data pointer register.

ONLY

PR0, PR1

Universal Pointer Register (PR0 represents R1,R2,R3; PR1 represents R5,R6,R7)

@PR0+d2

Universal memory location (0 - 16M) addressed indirectly via PR0 or PR1+ 2-bit

51MX

@PR1+d2

displacement (+0, +1, +2, +3).

#data2

2-bit constant included in instruction (value range: #1, #2, #3, #4).

addr23

23-bit destination address for HDATA or ECODE

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Chapter 2. Architecture Overview

ADDC

ADDC destination, source

CY

AC

N

OV

Z

Addition with Carry

X

X

X

X

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

ADDC

A,Rn

Add register to accumulator with carry flag

1

2

ADDC

A,dir8

Add direct byte to accumulator with carry flag

2

2

2

ADDC

A,@Ri

Add indirect RAM to accumulator with carry

1

2

flag

ADDC

A,#data8

Add immediate data to accumulator with carry

2

2

flag

AJMP

Absolute JUMP

CY

AC

N

OV

Z

—

—

—

—

—

Mnemonic

Description

Bytes

Bytes

Binary

Source

AJMP

addr11

Absolute Jump

2

2

DALLAS 24-Bit Contiguous Address Mode ONLY

AJMP

addr19

Absolute Jump

3

ANL

AND destination, source

CY

AC

N

OV

Z

Logical AND

—

—

X

—

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

ANL

A,Rn

AND register to accumulator

1

2

ANL

A,dir8

AND direct byte to accumulator

2

2

ANL

A,@Ri

AND indirect RAM to accumulator

1

2

ANL

A,#data8

AND immediate data to accumulator

2

2

ANL

dir,A

AND accumulator to direct byte

2

2

ANL

dir,#data8

AND immediate data to direct byte

3

3

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Chapter 2. Architecture Overview

CJNE

COMPARE destination, source

CY

AC

N

OV

Z

and jump if not equal

X

—

X

—

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

CJNE

A,dir8,rel

Compare dir byte to acc. and jump if not equal

3

3

CJNE

/A,#data8,rel

Compare imm. data to acc. and jump if not

3

3

2

equal

CJNE

Rn,#data8,rel

Compare imm. data to reg and jump if not

3

4

equal

CJNE

@Ri,#data8,rel

Compare imm. data to indir and jump if not

3

4

equal

CLR

CLEAR Operand

CY

AC

N

OV

Z

—

—

X

—

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

CLR

A

Clear accumulator

1

1

CLR

CLEAR Bit Operand

CY

AC

N

OV

Z

—

—

—

—

—

Mnemonic

Description

Bytes

Bytes

Binary

Source

CLR

C

Clear carry

1

1

CLR

bit8

Clear direct bit from BIT space

2

2

Intel/Atmel WM 251 ONLY

CLR

bit11

Clear direct bit from EBIT space

4

3

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Chapter 2. Architecture Overview

DA

DECIMAL ADJUST Accumulator

CY

AC

N

OV

Z

for Addition

X

—

X

—

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

DA

A

Decimal adjust accumulator

1

1

2

DEC

DECREMENT Operand with a

CY

AC

N

OV

Z

constant

—

—

X

—

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

DEC

A

Decrement accumulator

1

1

DEC

Rn

Decrement register

1

2

DEC

dir

Decrement dir byte

2

2

DEC

@Ri

Decrement indir RAM

1

2

Intel/Atmel WM 251 ONLY

DEC

Rm,#short

Decrement byte register with 1, 2 or 4

3

2

DEC

WRj,#short

Decrement word register with 1, 2 or 4

3

2

DEC

DRk,#short

Decrement double word register with 1, 2 or 4

3

2

DIV

DIVIDE Operands

CY

AC

N

OV

Z

0

—

X

X

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

DIV

AB

Divide A by B

1

1

Intel/Atmel WM 251 ONLY

DIV

Rm,Rm

Divide byte register by byte register

3

2

DIV

WRj,WRj

Divide word register by word register

3

2

DJNZ

DECREMENT Operand and Jump

CY

AC

N

OV

Z

if Not Zero

—

—

X

—

X

Mnemonic

Description

Bytes

Bytes

Binary

Source

DJNZ

Rn,rel

Decrement register and jump if not zero

2

3

DJNZ

dir8,rel

Decrement direct byte and jump if not zero

3

3