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Chapter 3. Writing Assembly Programs |
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Operands
Operands are arguments, or expressions, that are specified along with assembler directives or instructions. Assembler directives require operands that are constants or symbols. For example:
VVV |
EQU |
3 |
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DS |
10h |
Assembler instructions support a wider variety of operands than do directives. Some instructions require no operands and some may require up to 3 operands. Multiple operands are separated by commas. For example:
3 |
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MOV |
R2, #0 |
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The number of operands that are required and their types depend on the instruction or directive that is specified. In the following table the first four operands can also be expressions. Instruction operands can be classified as one the following types:
Operand Type |
Description |
Immediate Data |
Symbols or constants the are used as an numeric value. |
Direct Bit Address |
Symbols or constants that reference a bit address. |
Program Addresses |
Symbols or constants that reference a code address. |
Direct Data Addresses |
Symbols or constants that reference a data address. |
Indirect Addresses |
Indirect reference to a memory location, optionally with offset. |
Special Assembler Symbol |
Register names. |
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Shaded directives and options are available only in AX51 and A251.
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Special Assembler Symbols
The Ax51 assembler defines and reserves names of the x51 register set. These predefined names are used in x51 programs to access the processor registers. Following, is a list of the each of the 8051, 80C51MX, and 251 registers along with a brief description:
251 ONLY 51MX ONLY
Register Description
ARepresents the 8051 Accumulator. It is used with many operations including multiplication and division, moving data to and from external memory, Boolean operations, etc.
DPTR |
The DPTR register is a 16-bit data pointer used to address data in XDATA or |
3 |
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CODE memory. |
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PC |
The PC register is the 16-bit program counter. It contains the address of the |
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next instruction to be executed. |
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CThe Carry flag; indicates the status of operations that generate a carry bit. It is also used by operations that require a borrow bit.
AB The A and B register pair used in MUL and DIV instructions.
R0 – R7 The eight 8-bit general purpose 8051 registers in the currently active register bank. A Maximum of four register banks are available.
AR0 – AR7 Represent the absolute data addresses of R0 through R7 in the current register bank. The absolute address for these registers will change depending on the register bank that is currently selected. These symbols are only available when the USING directive is given. Refer to the USING directive for more information on selecting the register bank. These representations are suppressed by the NOAREGS directive. Refer to the NOAREGS directive for more information.
PR0, PR1 Universal Pointer Registers of the 80C51MX architecture. Universal Pointer can access the complete 16MB address space of the 80C51MX. PR0 is composed of registers R1, R2, and R3. PR1 is composed of registers R5, R6, and R7.
EPTR Additional extended data pointer register of the 80C51MX architecture. EPTR may be used to access the complete memory space.
R8 – R15 Additional eight 8–bit general purpose registers of the 251.
WR0 – Sixteen 16–bit general purpose registers of the 251. The registers WR0 - WR30 WR14 overlap the registers R0 - R15. Note that there is no WR1 available.
DR0 – DR28 Ten 32-bit general purpose registers of 251. The registers DR0 - DR28 overlap DR56, DR60 the registers WR0 - WR30. Note that there is no DR1, DR2 and DR3 available.
Shaded directives and options are available only in AX51 and A251.
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Chapter 3. Writing Assembly Programs |
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Immediate Data
An immediate data operand is a numeric expression that is encoded as a part of the machine language instruction. Immediate data values are used literally in an instruction to change the contents of a register or memory location. The pound (or number) sign (#) must precede any expression that is to be used as an immediate data operand. The following shows some examples of how the immediate data is typically used:
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MY_VAL |
EQU |
50H |
; an equate symbol |
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MOV |
A,IO_PORT2 |
; direct memory access to DATA |
3 |
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MOV |
A,#0E0h |
; load 0xE0 into the accumulator |
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MOV |
DPTR,#0x8000 |
; load 0x8000 into the data pointer |
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ANL |
A,#128 |
; AND the accumulator with 128 |
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XRL |
A,#0FFh |
; XOR A with 0ffh |
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MOV |
R5,#MY_VAL |
; load R5 with the value of MY_VAL |
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Memory Access
A memory access reads or writes a value in to the various memory spaces of the x51 system.
Direct memory access encodes the memory address in the instruction that to reads or writes the memory. With direct memory accesses you can access variables in the memory class DATA and BIT. For the 251 also the EDATA memory class is addressable with direct memory accesses.
Indirect memory accesses uses the content of a register in the instruction that reads or writes into the memory. With indirect address operands it is possible to access all memory classes of the x51.
The following examples show how to access the different memory classes of an x51 system.
Shaded directives and options are available only in AX51 and A251.
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DATA
Memory locations in the memory class DATA can be addressed with both: direct and indirect memory accesses. Special Function Registers (SFR) of the x51 have addresses above 0x80 in the DATA memory class. SFR locations can be addressed only with direct memory accesses. An indirect memory access to SFRs is not supported in the x51 microcontrollers.
Example for all 8051 variants
?DT?myvar |
SEGMENT |
DATA |
; define a SEGMENT of class DATA |
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RSEG |
?DT?myvar |
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VALUE: |
DS |
1 |
; reserve 1 BYTE in DATA space |
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3 |
IO_PORT2 |
DATA |
0A0H |
; special function register |
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VALUE2 |
DATA |
20H |
; absolute memory location |
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?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
A,IO_PORT2 |
; direct memory access to DATA |
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ADD |
A,VALUE |
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MOV |
VALUE2,A |
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MOV |
R1,#VALUE |
; load address of VALUE to R1 |
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ADD |
A,@R1 |
; indirect memory access to VALUE |
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BIT
Memory locations in the memory class BIT are addressed with the bit instructions of the 8051. Also the Special Function Registers (SFR) that are located bit-addressable memory locations can be addressed with bit instructions. Bit-addressable SFR locations are: 80H, 88H, 90H, 98H, 0A0H, 0A8H, 0B0H, 0B8H, 0C0H, 0C8H, 0D0H, 0D8H, 0E0H, 0E8H, 0F0H, and 0F8H.
Example for all 8051 variants
?BI?mybits SEGMENT |
BIT |
; define a SEGMENT of class BIT |
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RSEG |
?BI?mybits |
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FLAG: |
DBIT |
1 |
; reserve 1 Bit in BIT space |
P1 |
DATA |
90H |
; 8051 SFR PORT1 |
GREEN_LED |
BIT |
P1.2 |
; GREEN LED on I/O PORT P1.2 |
?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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SETB |
GREEN_LED |
; P1.2 = 1 |
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JB |
FLAG,is_on |
; direct memory access to DATA |
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SETB |
FLAG |
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CLR |
ACC.5 |
; reset bit 5 in register A |
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is_on: |
CLR |
FLAG |
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CLR |
GREEN_LED |
; P1.2 = 0 |
Shaded directives and options are available only in AX51 and A251.
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Chapter 3. Writing Assembly Programs |
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EBIT (only on Intel/Atmel WM 251)
The 251 provides with the EBIT memory class an expanded bit-addressable memory space that is addressed with extended bit instructions. Also all Special Function Registers (SFR) in the 251 can be addressed with extended bit instructions.
Example for Intel/Atmel WM 251
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?EB?mybits SEGMENT |
EBIT |
; define a SEGMENT of class EBIT |
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RSEG |
?EB?mybits |
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FLAG: |
DBIT |
1 |
; reserve 1 Bit in BIT space |
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CMOD |
DATA |
0D9H |
; PCA Counter Modes |
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3 |
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CPS0 |
BIT |
CMOD.1 |
; CPS0 bit |
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?PR?myprog |
SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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JB |
FLAG,is_on |
; direct memory access to DATA |
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SETB |
FLAG |
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: |
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is_on: |
CLR |
FLAG |
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CLR |
CPS0 |
; CMOD.1 = 0 |
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IDATA
Variables in this memory class are accessed via registers R0 or R1.
Example for all 8051 variants
?ID?myvars SEGMENT |
IDATA |
; define a SEGMENT of class IDATA |
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RSEG |
?EB?mybits |
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BUFFER: |
DS |
100 |
; reserve 100 Bytes |
?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
R0,#BUFFER |
; load the address in R0 |
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A,@R0 |
; read memory location buffer |
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INC |
R0 |
; increment memory address in R0 |
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MOV |
@R0,A |
; write memory location buffer+1 |
Shaded directives and options are available only in AX51 and A251.
Keil Software — A51/AX51/A251 Macro Assembler and Utilities |
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EDATA (Intel/Atmel WM 251, Philips 80C51MX only)
The EDATA memory is only available in the Philips 80C51MX and the
Intel/Atmel WM 251 architecture.
In the Philips 80C51MX, the EDATA memory can be accessed via EPTR or the Universal Pointers PR0 and PR1. Universal Pointers can access any memory location in the 16MB address space.
Example for Philips 80C51MX
?ED?my_seg SEGMENT |
EDATA |
; define a SEGMENT of class EDATA |
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RSEG |
?ED?my_seg |
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3 |
STRING: |
DS |
100 |
; reserve 100 Bytes |
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?PR?myprog |
SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
R1,#BYTE0 STRING |
; load address of STRING in PR0 |
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MOV |
R2,#BYTE1 STRING |
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MOV |
R3,#BYTE2 STRING |
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MOV |
A,@PR0 |
; load first byte of STRING in A |
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In the 251, EDATA memory can be accessed with direct memory addressing or indirect via the registers WR0 .. WR30. Also the memory class IDATA and DATA can be access with this addressing mode.
Example for Intel/Atmel WM 251
?ED?my_seg SEGMENT |
EDATA |
; define a SEGMENT of class EDATA |
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RSEG |
?ED?my_seg |
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STRING: |
DS |
100 |
; reserve 100 Bytes |
?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
R11,STRING+2 |
; load character at STRING[2] |
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WR4,#STRING |
; load address of STRING |
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MOV |
R6,@WR4 |
; indirect access |
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MOV |
@WR4+2,R6 |
; access with constant offset |
Shaded directives and options are available only in AX51 and A251.
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Chapter 3. Writing Assembly Programs |
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XDATA
The XDATA memory class can be accessed with the instruction MOVX via the register DPTR. A single page of the XDATA memory can be also accessed or via the registers R0, R1. At the C Compiler level this memory type is called pdata and the segment prefix ?PD? is used. The high address for this pdata page is typically set with the P2 register. But in new 8051 variants there are also dedicated special function registers that define the XDATA page address.
Example for all 8051 variants
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?XD?my_seg SEGMENT |
XDATA |
; define a SEGMENT of class XDATA |
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3 |
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RSEG |
?ED?my_seg |
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XBUFFER: |
DS |
100 |
; reserve 100 Bytes |
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?PD?myvars SEGMENT |
XDATA INPAGE |
; define a paged XDATA segment |
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RSEG |
?PD?myvars |
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VAR1: |
DS |
1 |
; reserve 1 byte |
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?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
P2,#HIGH ?PD?myvars |
; load page address register |
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: |
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MOV |
DPTR,#XBUFFER |
; load address |
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MOVX |
A,@DPTR |
; access via DPTR |
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MOV |
R1,#VAR1 |
; load address |
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MOVX |
@R1,A |
; access via R0 or R1 |
CODE and CONST
CODE or CONST memory can be accessed with the instruction MOVC via the DPTR register. The memory class CONST not possible with A51 and BL51.
Example for all 8051 variants
?CO?my_seg SEGMENT |
CODE |
; define a SEGMENT of class CODE |
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RSEG |
?CO?my_seg |
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TABLE: |
DB |
1,2,4,8,0x10 |
; a table with constant values |
?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
DPTR,#TABLE |
; load address of table |
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MOV |
A,#3 |
; load offset into table |
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MOVC |
A,@A+DPTR |
; access via MOVC instruction |
Shaded directives and options are available only in AX51 and A251.
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HDATA and HCONST
The HDATA and HCONST memory can be accessed with CPU instructions only in the Philips 80C51MX and the 251 architecture. HDATA and HCONST memory is simulated with memory banking on classic 8051 devices. The HDATA and HCONST memory class is not possible with A51 and BL51.
In the Philips 80C51MX, the HDATA and HCONST memory can be accessed via EPTR or the Universal Pointers PR0 and PR1. Universal Pointers can access any memory location in the 16MB address space.
Example for Philips 80C51MX
?HD?my_seg SEGMENT |
HDATA |
; define a SEGMENT of class HDATA |
3 |
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RSEG |
?HD?my_seg |
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ARRAY: |
DS |
100 |
; reserve 100 Bytes |
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?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
R1,#BYTE0 ARRAY |
; load address of ARRAY in PR0 |
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MOV |
R2,#BYTE1 ARRAY |
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MOV |
R3,#BYTE2 ARRAY |
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MOV |
A,@PR0 |
; load first byte of ARRAY in A |
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In the 251, HDATA and HCONST memory can be accessed via the registers DR0 .. DR28 and DR56. Any memory location can be accessed with this registers.
Example for Intel/Atmel WM 251
?HD?my_seg SEGMENT |
HDATA |
; define a SEGMENT of class HDATA |
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RSEG |
?HD?my_seg |
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ARRAY: |
DS |
100 |
; reserve 100 Bytes |
?PR?myprog SEGMENT |
CODE |
; define a segment for program code |
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RSEG |
?PR?myprog |
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MOV |
WR8,#WORD2 ARRAY |
; load address of ARRAY |
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MOV |
WR10,#WORD0 ARRAY |
; into DR8 |
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MOV |
R4,@DR8 |
; indirect access |
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MOV |
@DR8+50H,R4 |
; access with constant offset |
Shaded directives and options are available only in AX51 and A251.