Fundamentals of Microelectronics

VDD

R D

Vout

M 1 VDD

Vin

Figure 15.40

(a)Determine the output for Vin = 0 and Vin = VDD. Does the circuit invert?

(b)Can a trip point be obtained for this circuit?

8.In an NMOS inverter, (W=L)1 = 5=0:18 and RD = 2 k . Calculate the noise margins.

9.In Problem 8, we double the value of W=L or RD. Determine what happens to the noise margins in each case.

10.A more conservative definition of noise margins would use the input level at which the smallsignal gain reaches ,0:5 (rather than ,1). For an NMOS inverter with (W=L)1 = 5=0:18 and RD = 2 k , compute such noise margins and compare the results with those obtained in Problem 8.

11.Consider the inverter shown in Fig. 15.39, assuming (W=L)1 = 4=0:18 and (W=L)2 = 9=0:18. Calculate the noise margins.

12.Consider the cascade of identical NMOS inverters depicted in Fig. 15.41. If RD = 5 k , determine (W=L)1;2 such that the output low level of M1 (for Vin = VDD) is equal to NML

VDD

R D R D

Vout

Figure 15.41

of the second inverter. (In this situation, the output of the first inverter is degraded so much as to place the second stage at the point of unity gain.)

13. Two inverters having the characteristics shown in Fig. 15.42 are placed in a cascade. Sketch

the overall VTC of the cascade if (a) inverter A precedes inverter B, or (b) inverter B precedes inverter A.

Speed

14.An inverter is constructed as illustrated in Fig. 15.43, where Ron denotes the on-resistance of the switch. Assume Ron R2 so that the output low level is degraded negligibly.

(a) Compute the time required for the output to reach 95% of VDD if S1 turns off at t = 0.

VDD

R 2

Vout

Ron1 CL

A S 1

Figure 15.43

(b)Compute the time required for the output to reach 5% of VDD if S1 turns on at t = 0. How does the result compare with that in (a)?

15.An NMOS inverter must drive a load capacitance of 50 fF with an output resetime of 100 ps. Assuming the risetime is given by three output time constants, determine the maximum load resistor value.

16.An NMOS inverter with a load capacitance of 100 fF exhibits an output low level of 50 mV and an output risetime of 200 ps. Compute the load resistor and (W=L)1 if the risetime is given by three output time constants.

17.An NMOS inverter must drive a load capacitance of 100 fF while drawing a supply current of less than 1 mA when the output is low. What is the fastest risetime that the circuit can achieve? Assume the output low level is nearly zero.

18.In a CMOS inverter, (W=L)1 = 2=0:18 and (W=L)2 = 3=0:18. Determine the trip point of the circuit and the supply current drawn at this point.

19.For the inverter of Problem 18, calculate the small-signal voltage gain at the trip point if

N = 0:1 V,1 and P = 0:2 V,1.

20.Explain qualitatively what happens to the VTC of a CMOS inverter as the length of M1 or M2 is increased.

21.A CMOS inverter employs (W=L)1 = 3=0:18 and (W=L)2 = 7=0:18. Derive expressions for the VTC in each region of Fig. 15.19(d) and plot the result.

22.A CMOS inverter must provide a trip point equal to 0.5 V. Determine the required value of (W=L)1=(W=L)2. Note that a low trip point necessitates a strong NMOS device.

23.Explain why a CMOS inverter with the device parameters given at the beginning of this problem set cannot achieve a trip point of 0.3 V.

24.We often approximate the trip point of a CMOS inverter with the input voltage that places both transistors in saturation.

(a)Explain why this is a reasonable approximation if the inverter exhibits a high voltage gain around the trip point.

(b)Assuming (W=L)1 = 3=0:18 and (W=L)2 = 7=0:18, determine the minimum and maximum input voltages at which both transistors operate in saturation and calculate the difference between each and the trip point. Is the difference small?

25.Figure 15.44 shows three circuits along with three VTCs. Match the VTC with its corresponding circuit.

26.Due to a manufacturing error, a parasitic resistor RP = 2 K has appeared in the inverter of Fig. 15.45. If (W=L)1 = 3=0:18 and (W=L)2 = 5=0:18, calculate the low and high output levels and the trip point.

27.Calculate the small-signal voltage gain of the circuit in Problem 26 at the trip point with and without RP .

Figure 15.44

VDD

M 2

VinVout

M 1 RP

Figure 15.45

28.Calculate the noise margins for a CMOS inverter if (W=L)1 = 5=0:18 and (W=L)2 = 11=0:18.

29.Determine (W=L)1=(W=L)2 for a CMOS inverter if NML = 0:6 V. (Hint: solve the resulting equation by iteration.)

30.Consider Eq. (15.54) for VIL (= NML). Sketch the noise margin as a varies from 0 to infinity. Explain the results intuitively for very small and very large values of a.

31.Repeat Problem 30 for NMH.

32.Calculate the noise margins for the circuit in Problem 26.

33.Consider the circuit shown in Fig. 15.20(a), where Vout(t = 0) = 0. If (W=L)2 = 6=0:18 and CL = 50 fF, determine the time it takes for the output to reach VDD=2.

34.Repeat Problem 33 for the time it takes the output to reach 0:95VDD and compare the results.

35.In the circuit depicted in Fig. 15.23(a), the input jumps from 0 to V1 at t = 0. Assuming

Vout(t = 0) = VDD, (W=L)1 = 1=0:18, and CL = 30 fF, determine the time it takes the output to fall to VDD=2 if (a) V1 = VDD and (b) V1 = VDD=2.

36.Repeat Problem 35 for the time it takes the output to fall to 0:05VDD and compare the results.

37.A CMOS inverter with (W=L)1 = 1=0:18 and (W=L)2 = 3=0:18 drives a load capacitance of 80 fF. Calculate TPHL and TPLH.

38.Suppose the supply voltage in Problem 37 is raised by 10%. By how much do TPHL and TPLH decrease?

39.Repeat Problem 38 with VDD = 0:9 V and compare the results. Note the significant increase in TPHL and TPLH.

40.A CMOS inverter must achieve symmetric propagation delays equal to 80 ps while driving a load capacitance of 50 fF. Determine (W=L)1 and (W=L)2.

41.In Eq. (15.82), suppose VTH1 = 0:4 V. For what supply voltage do the two terms in the square brackets become equal? How should the supply voltage be chosen to make the first term 10% of the second?

42.A CMOS inverter with (W=L)1 = 1=0:18 exhibits a TPHL of 100 ps with CL = 80 fF. Determine the supply voltage.

43.We have received a CMOS inverter with unknown device dimensions and thresholds. Tests indicate TPHL = 120 ps with CL = 90 fF and VDD = 1:8 V, and TPHL = 160 ps with CL = 90 fF and V, VDD = 1:5 V. Determine (W=L)1 and VTH1.

44.In Eq. (15.82), the argument of the logarithm becomes negative if VDD < 4VTH1=3. Explain intuitively why this happens.

45.A 1-k resistor charges a capacitance of 100 fF from 0 V to VDD. Determine the energy dissipated in the resistor.

46.A digital circuit contains one million gates, and runs with a clock frequency of 2 GHz. Assuming that, on the average, 20% of the gates switch in every clock cycle, and the average load capacitance seen by each gate is 20 fF, determine the average power dissipation. Neglect the crowbar current. (Note that the result is unrealistically low because the crowbar current is neglected.)

47.An inverter using very wide transistors is used as a “clock buffer” in a microprocessor to deliver a 2-GHz clock to various flipflops. Suppose the buffer drives five million transistors with an average width of 1 m. If the gate length is 0.18 m, Cox = 10 fF= m2 and the gate capacitance is approximated by W LCox, determine the power dissipated by the clock buffer. Neglect the crowbar current (even though it is not negligible.)

48.The supply voltage of an inverter increases by 10%. If (W=L)1 = 2=0:18 and (W=L)2 = 4=0:18, determine the change in the peak crowbar current.

49.Approximating the crowbar current waveform in Fig. 15.29(c) with an isosceles triangle, calculate the average power dissipation resulting from this mechanism. Assume an operation frequency of f1.

50.A CMOS NOR gate drives a load capacitance of 20 fF. Suppose the input waveforms are as shown in Fig. 15.46, each having a frequency of f1 = 500 MHz. Calculate the power

A

B

t

Figure 15.46

dissipated by the gate. Neglect the crowbar current.

51.Repeat Problem 50 for a NAND gate.

52.For each NMOS section shown in Fig. 15.47, draw the dual PMOS section, construct the overall CMOS gate, and determine the logical function performed by the gate.

Design Problems

53.Design an NMOS inverter (i.e., determine RD and W=L) for a static power budget of 0.5 mW and an output low level of 100 mV.

Figure 15.47

54.Design an NMOS inverter (i.e., determine RD and W=L) for a static power budget of 0.25 mW and NML = 600 mV.

55.Design an NMOS inverter (i.e., determine RD and W=L) for an output low level of 100 mV and a power budget of 0.25 mW.

56.Determine (W=L)1;2 for a CMOS inverter such that the trip point is equal to 0.8 V and the current drawn from VDD at this point is equal to 0.5 mA. Assume n = 0:1 V,1 and

p = 0:2 V,1.

57.Is it possible to design a CMOS inverter such that NML = NMH = 0:7 V if VTH1 =6 jVTH2j? Explain why?

58.Determine (W=L)1;2 for a CMOS inverter such that TPLH = TPHL = 100 ps while the circuit drives a load capacitance of 50 fF.

SPICE Problems

In the following problems, use the MOS device models given in Appendix A.

59.The inverter of Fig. 15.48 must provide a trip point at 0.8 V. If (W=L)1 = 0:6 m=0:18 m, determine (W=L)2. Also, plot the supply current as a function of Vin for 0 < Vin < 1:8 V.

VDD = 1.8 V

M 2

VinVout

M 1

Figure 15.48

60. The inverter cascade shown in Fig. 15.49 drives a load capacitance of 100 fF. Assume W1 =

0:5W2 = 0:6 m, W3 = 0:5W4, and L = 0:18 m for all four devices.

(a) Determine the optimum choice of W3 (and W4) if the total delay from Vin to Vout must be minimized. What is the delay contribution of each stage?

Figure 15.49

(b) Determine the average power dissipation of the circuit at a frequency of 500 MHz.

61. Consider a CMOS NAND gate with its inputs shorted together so as to form an inverter (Fig.

15.50. We wish to determine the delay of this circuit with a fanout of four; i.e., if it is loaded

VDD = 1.8 V

Vout

VinM 2

M 1

Figure 15.50

by a similar stage that incorporates devices whose width is scaled up by a factor of four. Use SPICE to compute this delay.

62.Repeat Problem 61 for a NOR gate and compare the results.

63.The circuit depicted in Fig. 15.51 is called a “ring oscillator.” Assuming VDD = 1:8 V and

X Y Z

Figure 15.51

W=L = 2 m=0:18 m for the NMOS devices, select W=L for the PMOS transistors such that the frequency of oscillation is maximized. (To start the oscillation in SPICE, you must apply an initial condition to one of the nodes, e.g., .ic v(x)=0.)

Introduction to SPICE

The circuits encountered in microelectronics may contain a few devices or a few million devices.1 How do we analyze and design these circuits? As the number of devices in a circuit increases, hand analysis becomes more difficult, eventually reaching a point where other methods are required. For example, one can build a prototype using discrete components and observe its behavior. However, discrete devices provide a poor approximation of modern integrated circuits. Furthermore, even for a few hundred devices, discrete prototypes become prohibitively complex.

Today's microelectronics employs simulation programs extensively. A versatile tool used to predict the behavior of circuits is Simulation Program with Integrated Circuit Emphasis (SPICE). While orginally developed as a public-domain tool (at University of California, Berkeley), SPICE has evolved into commercial tools such as PSPICE, HSPICE, etc., most of which retain the same format. This appendix provides a tutorial overview of SPICE, enabling the reader to perform basic simulations. More details can be found in [1].

A.1 Simulation Procedure

Suppose we have the circuit shown in Fig. A.1(a) and wish to use SPICE to study its frequency response. That is, we wish to verify that the response is relatively flat for f < 1=(2 R1C1) 15:9 MHz and begins to roll off thereafter [Fig. A.1(b)]. To this end, we apply a sinusoidal voltage to the input and vary its frequency from, say, 1 MHz to 50 MHz.

The procedure consists of two steps: (1) define the circuit in a language (format) that SPICE understands, and (2) use an appropriate command to tell SPICE to determine the frequency response. Let us begin with the first step. This step itself consists of three tasks.

(1)Label each node in the circuit. Figure A.1(c) depicts an example, where the labels “in” and “out” refer to the input and output nodes, respectively. The common (ground) node must be called “0” in SPICE. While arbitrary, the labels chosen for other nodes should carry some information about their respective nodes so as to facilitate reading the SPICE description of the circuit.

(2)Label each element in the circuit. Defining the type of the element (resistors, capacitors, etc.), each of these labels must begin with a specific letter so that SPICE recognizes the element. For example, resistor labels must begin with r, capacitor labels with c, inductor labels with l, diode labels with d, and voltage sources with v.2 Our simple circuit now appears as shown in Fig. A.1(d).

1Recent microprocessors contain one billion MOS transistors.

2SPICE does not distinguish between lower-case and upper-case letters.

817

Figure A.1 (a) Simple RC circuit, (b) its frequency response, (c) with nodes labeled, (d) with elements labeled.

(3) Construct the “netlist,” i.e., a precise description of each element along with the nodes to which it is tied. The netlist consists of text lines, each describing one element, with the following format for two-terminal devices:

elementlabel node1 node2 value

From the example in Fig. A.1(d), we begin the netlist with:

r1 in out 1k

c1 out 0 10p

Note that the units are specified as a single letter (k for 103, p for 10,12, etc.). For the input voltage source, we write

vin in 0 ac 1

where ac denotes our desire to determine the frequency (ac) response and hence designates Vin as a sinusoidal voltage source whose frequency will be varied. The value 1 at the end represents the peak amplitude of the sinusoid. Also note that the first node, “in,” is assumed to be the positive terminal of the voltage source.

The netlist must also include the “type of analysis” that we wish SPICE to perform. In our example, SPICE must vary the frequency from one value to another, e.g., 1 MHz to 50 MHz. The corresponding command appears as

.ac dec 200 1meg 50meg

Note that each “command” line begins with a period. The first entry, “ac,” requests SPICE to perform an “ac analysis,” i.e., determine the frequency response. The second and third entries, “dec 200,” tell SPICE to simulate the circuit at 200 frequency values in every decade of frequency (e.g., from 1 MHz to 10 MHz). The last two entries, “1meg 50meg,” set the lower and upper

confused with “m,” which stands for 103.

We need two more lines to complete our netlist. The first line of the file is called the “title” and carries no information for SPICE. For example, the title line may read “My Amplifier.” Note that SPICE always ignores the first line of the file, encountering errors if you forget include the title. The last line of the file must be a “.end” command. Our netlist now appears as:

Test Circuit for Frequency Response r1 in out 1k

c1 out 0 10p vin in 0 ac 1

.ac dec 200 1meg 50 meg

.end

Note that, except for the first and last lines, the order of other lines in the netlist is unimportant. What do we do with the above netlist? We must “run” SPICE on this file, which we call, for

example, test.sp. Depending on the operating system, running SPICE may entail clicking on an icon in a graphics interface or simply typing:

spice test.sp

After the simulation is successfully run, various node voltages can be plotted using the graphics interface that accompanies SPICE.

Figure A.2 summarizes the SPICE simulation procedure. The definition of (voltage or current) sources in the netlist must be consistent with the type of analysis. In the above example, the input

Source Definitions

.Type of Analysis

.end

Figure A.2 Simulation procedure.

voltage source definition contains the entry “ac” so that SPICE applies the frequency sweep to Vin rather than other sources.

At this point, the reader may raise many questions: How are other elements defined in the netlist? How are the units specified? Is the order of the node labels in the netlist important? How are other types of analysis specified? We answer these questions in the following sections.

A.2 Types of Analysis

In addition to frequency response, other aspects of circuits may also be of interest. This section provides the (voltage or current) source descriptions and commands necessary to perform other

types of analysis.

A.2.1 Operating Point Analysis

In many electronic circuits, we must first determine the bias conditions of the devices. SPICE performs such an analysis with the .op command. The following example illustrates the procedure.

Example A.1

Determine the currents flowing through R3 and R4 in Fig. A.3(a).

Figure A.3

Solution

We label the nodes as shown in Fig. A.3(b) and construct the netlist as follows:

Simple Resistive Network v1 batt 0 1.5

r1 batt x 1k

r2 x y 2k

r3 y 0 2k

r4 y 0 3k

.op

.end

SPICE predicts a current of 0.214 mA through R3 and 0.143 mA through R4.

A.2.2 Transient Analysis

Suppose we wish to study the pulse response of the RC section shown in Fig. A.1(d). Called “transient analysis,” this type of simulation requires changing the vin and .ac lines while maintaining the same netlist descriptions for R1 and C1. The voltage source must now be specified as

V1 V2 Tdel Tr Tf Tw

where V1, ..., Tw are defined as depicted in Fig. A.4(a). 3 We say Vin is a pulse that goes from 0

3The parentheses following the pulse description are for clarity and not essential.