Fundamentals of Microelectronics

pulling the output node to VDD [Fig. 15.18(b)].

As Vin rises, the gate-source overdrive of M2 decreases and its on-resistance increases. But, for Vin < VTH1, M1 remains off and Vout = VDD. As Vin exceeds VTH1 slightly, M1 turns on, drawing a current from VDD through the on-resistance of M2 [Fig. 15.18(c)]. Since Vout is still close to VDD, M1 operates in saturation and M2 still resides in the triode region. Equating the drain currents of the two, we have

12 nCox( WL )1(Vin , VTH1)2 =

12 pCox( WL )2[2(VDD , Vin , jVTH2j)(VDD , Vout) , (VDD , Vout)2]; (15.43)

where channel-length modulation is neglected. This quadratic equation can be solved in terms of VDD , Vout to express the behavior of Vout as a function of Vin. But from a qualitative point of view, we observe that Vout continues to fall as Vin rises because both ID1 and the channel resistance of M2 increase.

If Vout falls sufficiently, M2 enters saturation. That is, if Vout = Vin + jVTH2j, then M2 is about to exit the triode region. But how about M1? Since the drain voltage of M1 (=Vout) is higher than its gate voltage (Vin), this device still operates in saturation. To obtain the inverter VTC in this region, we equate the drain currents again and neglect channel-length modulation:

What happened to Vout here?! Equation 15.44 is meaningless as it does not contain Vout and implies a unique value for Vin. This quandary arises because we have allowed two ideal current sources fight each other at the output node. Inclusion of channel-length modulation resolves this issue:

To gain more insight and prove that Vout changes sharply here, let us compute the smallsignal gain of the inverter in this region. Operating is saturation, each transistor can be modeled as a voltage-dependent current source with a finite output impedance [ Fig. 15.18(d)]. Since v2 = v1 = vin, a KCL at the output node yields

indicating that the voltage gain is on the order of the intrinsic gain of a MOSFET. Thus, for a small change in Vin, we expect a large change in Vout.

Figure 15.19(a) summarizes our findings this far. The output remains at VDD for Vin < VTH1,

M 1 Off, M 2 in Triode Region

M 1 Off, M 2 in Triode Region

Figure 15.19 (a) Behavior of CMOS inverter for Vin VinT , (b) CMOS inverter at trip point, (c) M1 at the edge of saturation, (d) overall characteristic.

begins to fall as Vin exceeds VTH1, and experiences a sharp drop when M2 enters saturation. The input level at which Vout = Vin is called the “trip point” (also called the “switching threshold”) of the inverter [Fig. 15.19(b)]. Both transistors are in saturation at this point (why?). The trip point is denoted by VM . Also, the maximum and minimum values of a gate output are denoted by VOH and VOL, respectively.

As the input goes beyond the trip point, Vin , Vout eventually exceeds VTH1, thereby driving M1 into the triode region. The transconductance of M1 therefore falls and so does the smallsignal gain of the circuit [Fig. 15.19(c)]. We now have

where channel-length modulation is neglected. From this quadratic equation, Vout can be expressed in terms of Vin, but we expect a more gradual slope due to the operation of M1 in the triode region.

Finally, as Vin rises to VDD ,jVTH2j, M2 turns off, allowing Vout = 0. In this region, M1 acts as a resistor carrying a zero current. Figure 15.19(d) plots the overall VTC, identifying different regions of operations by numbers.

Example 15.14

Determine a relationship between (W=L)1 and (W=L)2 that sets the trip point of the CMOS inverter to VDD=2, thus providing a “symmetric” VTC.

Solution

Replacing both Vin and Vout with VDD=2 in Eq. (15.45), we have

nCox( WL )1(VDD2 , VTH1)2(1 + 1 VDD2 ) = pCox(WL )2( VDD2 , jVTH2j)2(1 + 2 VDD2 );

(15.49)

and hence

In practice, the difference between jVTH2j and VTH1 can be neglected with respect to VDD=2 , jVTH1;2j. Similarly, 1 + 1VDD=2 1 + 2VDD =2. Also, in digital design, both L1 and L2 are typically chosen equal to the minimum allowable value. Thus,

Since the PMOS mobility is about one-third to one-half of the NMOS mobility, M2 is typically twice to three times as wide as M1.

Exercise

What is the small-signal gain of the inverter under this condition?

Example 15.15

Explain qualitatively what happens to the VTC of the CMOS inverter as the width of the PMOS transistor is increased (i.e., as the PMOS device is made “stronger”)?

Solution

Let us first consider the transition region around the trip point, where both M1 and M2 operate in saturation. As the PMOS device is made stronger, the circuit requires a higher input voltage to establish ID1 = jID2j. This is evident from Eq. (15.45): for Vout = VDD=2, as (W=L)2 increases, Vin must also increase so that (VDD ,Vin ,jVTH2j)2 on the right hand side decreases and (Vin , VTH1)2 on the left hand side increases. Consequently, the characteristic is shifted to the right (why?). (What happens to the small-signal gain near the trip point?)

Exercise

What happens to the VTC of the CMOS inverter if the PMOS device experiences resistive

degeneration?

Noise Margins Recall from Example 15.6 that a digital inverter always exhibits a smallsignal voltage gain greater than unity in some region of the input/output characteristic. Since the gain of a CMOS inverter falls to zero near Vin = 0 and Vin = VDD (why?), we expect a gain of (negative) unity at two points between 0 and VDD.

To determine the noise margin for logical low levels, we focus on region 2 in Fig. 15.19(d). With M2 in the triode region, the voltage gain is relatively low and likely to assume a magnitude of unity somewhere. How do we express the gain of the circuit here? In a manner similar to Example 15.7, we directly differentiate both sides of (15.43) with respect to Vin:

where VOH denotes the corresponding output level. Obtaining VOH from (15.53), substituting in (15.43), and carrying out some lengthy algebra, we arrive at

Solution

Choice of a = 1 in (15.54) yields VIL = 1 , 1. We can use L'Hopital's rule by first writing (15.54) as

where it is assumed VTH1 = jVTH2j. Differentiating the numerator and the denominator with respect to a and substituting 1 for a, we have

Exercise

Explain why VIL must always exceed VTH1.

We now turn our attention to NMH and differentiate both sides of (15.48) with respect to Vin:

Example 15.17

Compare the noise margins expressed by (15.60) with those of an ideal inverter.

Solution

An ideal inverter is characterized by the behavior illustrated in Fig. 15.1(b), where the smallsignal gain goes abruptly from zero to infinity at the trip point. With a symmetric VTC,

This value is greater than that in (15.60) because VTH1 and jVTH2j are typically less than VDD=2 (and the gain in the transition region less than infinity).

Exercise

Determine the reduction in the noise margins of an ideal inverter if its transition region gain is equal to 5. Assume a symmteric VTC.

Example 15.18

Explain what happens if VTH1 and jVTH2 in a CMOS inverter exceed VDD=2.

Solution

Consider the operation of the circuit for Vin = VDD=2. In this case, both transistors are off, allowing the output node to “float.” For this and speed reasons (explained in the next section), the threshold voltage is typically chosen to be less than VDD=4.

796 Chap. 15 Digital CMOS Circuits

Exercise

What happens if VTH1 = VDD=4 but jVTH2j = 3VDD=4?

15.2.3 Dynamic Characteristics

As explained in Section 15.1.2, the dynamic behavior of gates related to the rate at which their output can change from one logical level to another. We now analyze the response of a CMOS inverter to a step input while the circuit drives a finite load capacitance. Our study of the NMOS inverter in Section 15.1.2 and the contrasts drawn in Section 15.2.1 prove useful here.

Qualitative Study Let us first understand qualitatively how a CMOS inverter charges and discharges a load capacitance. Suppose, as depicted in Fig. 15.20(a), Vin jumps from VDD to

Figure 15.20 (a) CMOS inverter charging a load capacitance, (b) output waveform.

0 at t = 0 and Vout begins to from 0. Transistor M1 turns off and transistor M2 turns on in saturation., charging CL toward VDD. With the relatively constant current provided by M2, Vout rises linearly until M2 enters the triode region and hence supplies a smaller current. The output voltage continues to rise, almost as if M2 acts as a resistor, eventually approaching VDD and forcing the drain current of M2 to zero. Figure 15.20(b) sketches the behavior of the output.

Example 15.19

Sketch the drain current of M2 as a function of time.

Solution

The current begins at a high (saturated) value and begins to fall as Vout exceeds jVTH2j (why?). Thereafter, the current continues to drop as Vout approaches VDD and hence VDS2 falls to zero. Figure 15.21 plots the result.

Exercise

Sketch the supply current as a function of time.

Example 15.20

Sketch the output waveform of Fig. 15.20(b) for different values of (W=L)2.

Solution

As (W=L)2 increases, so does the current drive of M2 (in both saturation and triode regions).

Vout

VDD

M 2 in Triode Region

VTH2

I D2

t

Figure 15.21

The circuit therefore exhibits a faster rising transition, as illustrated in Fig. 15.22. Of course, for

very large values of W2, the capacitance contributed by M2 itself at the output node becomes comparable with CL, and the speed improves to a lesser extent.

Exercise

Sketch the drain current of M2 for different values of (W=L)2.

How about the output discharge behavior? As shown in Fig. 15.23(a), if the input steps from

Figure 15.23 (a) CMOS inverter discharging a load capacitance, (b) output waveform.

0 to VDD at t = 0, M2 turns off, M1 turns on, beginning to discharge CL from VDD toward 0. Transistor M1 operates in saturation until Vout falls by VTH1 below the gate voltage (= VDD), upon which ID1 begins to decrease, slowing down the discharge. Plotted in Fig. 15.23(b), Vout then gradually approaches zero.

798 Chap. 15 Digital CMOS Circuits

Quantitative Analysis With the insights developed above, we can now quantify the rising and falling transitions at the output of the CMOS inverter, thereby arriving at the propagation delays. We neglect channel-length modulation here.

Recall from Fig. 15.20 that, after the input falls to zero, M2 begins to charge CL with a

where the origin of time is chosen to coincide with t = TPLH1 for simplicity, and TPLH2 denotes

Interestingly, the denominator of (15.71) represents the inverse of the on-resistance of M2 when it operates in the deep triode region. Thus,

If 4jVTH2j VDD, this result reduce s to TPLH2 = Ron2CL ln 2 —as if CL charges up through a constant resistance equal to Ron2. The overall propagation delay is therefore given by

An important observation here is that TPLH decreases as VDD increases (why?). Also, for jVTH2j VDD=4, the two terms inside the square brackets are nearly equal.

Example 15.21

A student decides to avoid the foregoing derivation of TPLH2 through the use of an average current for M2. That is, ID2 can be approximated as a constant value equal to the average between its initial value, (1=2) pCox(W=L)2(VDD ,jVTH2j)2, and its final value, 0. Determine the resulting TPLH2 and compare with that expressed by (15.72).

Solution

Assuming jVTH2j is roughly equal to VDD=4 and hence VDD=(VDD , jVTH2j) 4=3, we have

(1=2) nCox(W=L)1(VDD , VTH1j)2. The time required for M1 to enter the triode region is thus given by

800 Chap. 15 Digital CMOS Circuits

where the negative sign on the right accounts for the flow of the current out of the capacitor. Using (15.69) to solve this differential equation and bearing in mind that Vout(t = 0) = VDD , VTH1, we obtain

which, of course, has the same form as (15.72). Also, the total delay is given by

Example 15.22

Compare the two terms inside the square brackets in (15.82) as VTH1 varies from zero to VDD=2.

Solution

For VTH1 = 0, the first term is equal to 0 and and the second equal to ln 3 1:1. As VTH1 increases, the two terms converge, both reaching 0.684 for VTH1 = 0:255VDD. Finally, for VTH1 = VDD=2,, the first term rises to 2 and the second falls to 0. Figure 15.24 plots each term

Second

Term

0.255VDD 0.5VDD VTH

Figure 15.24

and the sum of the two, suggesting that low thresholds improve the speed.

Exercise

Repeat the above example if VTH1 varies from 0 to 3VDD=4.

Example 15.23

Due to a manufacturing error, an inverter is constructed as shown in Fig. 15.25, where M10 appears in series with M1 and is identical to M1. Explain what happens to the output falltime. For simplicity, view M1 and M10 as resistors when they are on.