Fundamentals of Microelectronics

VDD

M 2

VinVout

M 1

M 1'

Figure 15.25

Solution

Placing the two on-resistances in series, we have

Thus, the falltime is doubled.

Exercise

What happens if M10 is twice as wide as M1?

15.2.4 Power Dissipation

Having determined the propagation delays of the CMOS inverter, we now turn our attention to the power dissipation of the circuit. Unlike the NMOS inverter, this type of logic consumes no static power. We therefore need only study the behavior of the circuit during transitions and determine the “dynamic” power dissipation. Let us first assume abrupt transitions at the input.

If the input voltage jumps from VDD to 0, then the PMOS device charges the load capacitance toward VDD [Fig. 15.26(a)]. As Vout approaches VDD, the energy stored in CL is equal to

Figure 15.26 Power consumed in transistors during (a) charge and (b) discharge of load capacitance.

802 Chap. 15 Digital CMOS Circuits

This energy is supplied by M2 from VDD. On the other hand, if Vin steps from 0 to VDD, then the NMOS transistor discharges CL toward zero [Fig. 15.26(b)]. That is, the energy E1 is removed from CL and dissipated by M1 in the discharge process. This cycle repeats for every pair of falling and rising transitions at the input.

In summary, for every pair of falling and rising transitions at the input of the inverter, CL

acquires and loses an energy of (1=2)CLV 2 . For a periodic input, we may then surmise that

DD

the circuit consumes an average power of (1=2)CLV 2 =Tin, where Tin denotes the input period.

DD

Unfortunately, this result is incorrect. In addition to delivering energy to CL, the PMOS transistor in Fig. 15.26(a) also consumes power because it carries a finite current while sustaining a finite voltage. In other words, the total energy drawn from VDD in Fig. 15.26(a) consists of that stored on CL plus that dissipated in M2.

How do we compute the energy consumed by M2? We first observe that (a) the instantaneous power dissipated in M2 is given by jVDS2jjID2j = (VDD , Vout)jID2j, and (b) this transistor charges the load capacitor and hence jID2j = CLdVout=dt. To calculate the energy lost in M2, we must integrate the instantaneous power dissipation with respect to time:

Interestingly, the energy consumed by M2 is equal to that stored on CL. Thus, the total energy drawn from VDD is

It follows that, for a periodic input with frequency fin, the average power drawn from VDD is equal to

Example 15.24

In the circuit of Fig. 15.27, Vout = 0 at t = 0. Compute the energy drawn from the supply as

VDD

RL

Vout

CL

Figure 15.27

Vout reaches VDD.

Solution

We note that the derivation leading to Eq. (15.91) is completely general and independent of the I/V characteristics of the device that charges CL. In other words, the circuit of Fig. 15.27 stores

Exercise

Compute the energy consumed by RL.

Equation (15.92) plays a central role in CMOS logic design, elegantly expressing the dependence of Pav on the data rate, the load capacitance, and the supply voltage. The square dependence on VDD calls for the reduction of the supply voltage, whereas Eqs. (15.74) and (15.82) for the propagation delays favor raising VDD.

Power-Delay Product As mentioned in Section 15.1.3, the power-delay product represents the trade-off between the power dissipation and the speed. With the aid of Eqs. (15.35), (15.74), and (15.82) and assuming that TPHL and TPLH are roughly equal, we write

Interestingly, the PDP is proportional to C2 , underlining the importance of minimizing capaci-

L

tances in the circuit.

Example 15.25

In the absence of long interconnects, CL in Fig. 15.26 arises only from transistor capacitances. Consider a cascade of two identical inverters, Fig. 15.28, where the PMOS device is three

VDD

VinVout

Figure 15.28

times as wide as the NMOS transistor to provide a symmetric VTC. For simplicity, assume the capacitance at node X is equal to 4W LCox. Also, VTHN = jVTHP j VDD =4. Compute the PDP.

Solution

We have

Also, from Example 15.22, the two terms in the square brackets in (15.74) and (15.82) add up to 1.36. Thus, (15.93) reduces to

7:25W L2CoxfinV 2

P DP = DD : (15.96)

n

Exercise

Suppose the withs of all four transistors are doubled. Does the delay of the first inverter change? How about the power dissipated per transition? From these observations, explain why P DP is linearly proportional to W .

Crowbar Current In our study of the dynamic power consumption, we have assumed abrupt transitions at the input. In practice, however, the input suffers from a finite transition time, thereby leading to another dissipation component.

Recall from the VTC of Fig. 15.19(d) that both transistors in an inverter are on in regions 2, 3, and 4. That is, if the input lies in the range [VTH1 VDD ,jVTH2j], then M2 draws a current from VDD and M1 passes this current to ground —as if a direct path conducts current from VDD to ground [Fig. 15.29(a)]. Called the “crowbar current,” this component arises each time the input

(c)

Figure 15.29 (a) Crowbar current drawn by CMOS inverter, (b) time period during which crowbar current is drawn, (c) crowbar current as a function of time and Vin.

swings from one rail to the other with a finite transition time. As illustrated in Fig. 15.29(b), the circuit draws a crowbar current from t1 to t2.

How does the crowbar current very between t1 and t2 in Fig. 15.29(b)? For Vin slightly above VTH1, M1 is barely on, drawing only a small current. As Vin approaches the trip point of the inverter, both transistors enter saturation and the crowbar current reaches a maximum. Finally, as Vin reaches VDD , jVTH2j, the crowbar current returns to zero. Figure 15.29(c) plots the behavior fo this current as a function of t and Vin. The peak value is obtained by assuming

Vin = Vout = VDD =2 in either side of Eq. (15.45):

15.3 CMOS NOR and NAND Gates

The CMOS inverter serves as the foundation for realizing other logical gates. In this section, we study NOR and NAND gates, both of which find wide application.

15.3.1 NOR Gate

Recall from basic logic design that the OR operation, A + B, produces a high output if at least one input is high. The NOR gate, A + B, thus generates a low output if at least one input is high.

How should a CMOS inverter be modified to serve as a NOR gate? First, we need two sets of NMOS and PMOS devices that are controlled by the two inputs. Second, considering the NMOS section first, we note that if one of the NMOS gates is high, the output (the drain voltage) must remain low. We then surmise that the NMOS section can be realized as shown in Fig. 15.30, recognizing that, if A or B is high, the corresponding transistor is on, pulling Vout to zero.

Vout

A M 1 B M 2

Figure 15.30 NMOS section of a NOR gate.

This, of course, occurs only if the remainder of the circuit (the PMOS section) “cooperates,” as observed for the inverter in Section 15.2.1.

Example 15.26

Excited by the simple realization in Fig. 15.30, a student decides that the PMOS section should incorporate a similar topology, thus arriving at the circuit depicted in Fig. 15.31(a). Explain why

Figure 15.31

this configuration does not operate as a NOR gate.

Solution

Recall from Section 15.2.1 that cooperation between the NMOS and PMOS sections means that when one is on, the other must remain off. Unfortunately, the circuit of Fig. 15.31(a) fails to satisfy this principle. Specifically, if A is high and B is low, then both M1 and M4 are on [Fig. 15.31(b)], “fighting” each other and producing an ill-defined logical output. (Also, the circuit draws significant static power from VDD).

Exercise

What happens if M4 is omitted?

The above example reveals that the PMOS section must remain off if A or B (or both) are high. Moreover, if both inputs are low, the PMOS section must be on so as to ensure Vout is pulled up to VDD. Shown in Fig. 15.32(a) is such a circuit, blocking the path from VDD to Vout

VDD

Figure 15.32 (a) PMOS section of a NOR gate, (b) complete CMOS NOR gate.

if one of the inputs is high (why?), but raising Vout to VDD if both inputs are low. The operation, of course, remains unchanged if A and B are swapped.

Figure 15.32(b) depicts the overall CMOS NOR implementation. The reader is encouraged to verify the operation for all four input logical combinations and prove that the circuit consumes no static power.

The reader may wonder why we did not attempt to implement an OR gate. As evident from the foregoing development, the evolution of the circuit from a CMOS inverter inherently contains an inversion. If an OR gate is necessary, the topology of Fig. 15.32(b) can be followed by an inverter.

Example 15.27

Construct a three-input NOR gate.

Solution

We expand the NMOS section of Fig. 15.30 and the PMOS section of Fig. 15.32(a) so as to accommodate three inputs. The result is depicted in Fig. 15.33.

VDD

M 6

M 5

M 4

Vout

A M 1 B M 2 C M 3

Figure 15.33

Exercise

Study the behavior of the circuit if M3 is accidentally omitted.

The principal drawback of the CMOS NOR gate stems from the use of PMOS devices in series. Recall that the low mobility of holes requires a proportionally wider PMOS transistor to obtain a symmetric VTC and, more importantly, equal rise and fall times. Viewing the transistors in a two-input NOR gate as resistors for simplicity, we observe that the PMOS section suffers from twice the resistance of each PMOS device (Example 15.23), creating a slow rising transition at the output (Fig. 15.34). If wider PMOS transistors are employed to reduce Ron, then their gate

VDD

M 4

2 Ron

M 3

Vout

Figure 15.34 PMOS devices in series charging a load capacitance.

capacitance ( W LCox) increases, thereby loading the preceding stage. The situation worsens as the number of inputs to the gate increases.

Example 15.28

Select the relative widths of the transistors in the three-input NOR gate of Fig. 15.33 for equal rise and fall times. Assume n 2 p and equal channel lengths.

Solution

The series combination of the three PMOS devices must present a resistance equal to that of an NMOS transistor. If W1 = W2 = W3 = W, then we must choose

so as to ensure that each PMOS device exhibits an on-resistance equal to one-third of that of each NMOS transistor. Note that the gate presents a capacitance of about 7W LCox at each input, quite larger than that of an inverter ( 3W LCox).

Exercise

Repeat the above example if n 3 p.

15.3.2 NAND Gate

The developments in Section 15.3.1 for the NOR gate can readily be extended to create a NAND gate. Since an NAND operation, A B, produces a zero output if both inputs are high, we con-

808 Chap. 15 Digital CMOS Circuits

struct the NMOS section as shown in Fig. 15.35(a), where M1 or M2 blocks the path from Vout

Figure 15.35 (a) NMOS section of a NAND gate, (b) PMOS section of a NAND gate, (c) complete CMOS NAND gate.

to ground unless both A and B remain high. The PMOS section, on other hand, must pull Vout to VDD if at least one of the inputs is low, and is thus realized as shown in Fig. 15.35(b). Figure 15.35(c) depicts the overall NAND gate. This circuit, too, consumes zero static power.

In contrast to the NOR gate, the NAND gate places NMOS devices in series, thus suffering less severely from speed limitation of PMOS transistors. The following example illustrates this point.

Example 15.29

Design a three-input NAND gate and determine the relative widths of the transistors for equal rise and fall times. Assume n 2 p and equal channel lengths.

Solution

Figure 15.36 shows the realization of the gate. With three NMOS transistors in series, we select

Figure 15.36

a width of 3W for M1-M3 so that the total series resistance is equivalent to one device having a width of W . Each PMOS device must therefore have a width of 2W . Consequently, the capacitance seen at each input is roughly equal to 5W LCox, about 30% less than that of the NOR gate in Example 15.28.

Exercise

Repeat the above example if n 3 p.

In CMOS logic, the PMOS and NMOS sectios are called “dual” of each other. In fact, given one section, we can construct the other according to the following rule: convert each series branch to parallel branches and vice versa.

Example 15.30

Determine the PMOS dual of the circuit shown in Fig. 15.37(a) and determine the logical function performed by the overall CMOS realization.

Figure 15.37

Solution

Here, M1 and M2 are placed in series (to perform a NAND operation) and the combination appears in parallel with M3 (to implement a NOR function). The PMOS dual therefore consists of a parallel combination of two transistors, and a third transistor in series with this combination [Fig. 15.37(b)]. Figure 15.37(c) depicts the overall gate, which performs the logical function

A B + C.

Exercise

Suppose M3 is accidentally omitted. Study the behavior of the gate.

15.4 Chapter Summary

Noise margin is defined as the voltage degradation on the high or low levels that places the signal at the unity-gain point of the input/output characteristic.

The speed of gates is given by the drive capability of the transistors and the capacitances contributed by transistors and interconnecting wires.

The NMOS and PMOS devices in an inverter provide “active” pull-down and pull-up currents and hence enhance each other's operation.

Problems

Unless otherwise stated, in the following problems assume VDD = 1:8 V, nCox = 100 A=V2,

pCox = 50 A=V2, VTH;N = 0:4 V, VTH;P = ,0:5 V, N = 0, and P = 0.

1.In the CS stage of Example 15.2, we have RD = 10 k and (W=L)1 = 3=0:18. Calculate the output low level when Vin = VDD.

2.The CS stage of Example 15.2 must achieve an output low level no higher than 100 mV. If RD = 5 k , determine the minimum required value of (W=L)1.

3.Consider the PMOS common-source stage shown in Fig. 15.38. We wish to utilize this circuit

VDD

Vin M 1

Vout

RD

Figure 15.38

as a logical inverter. Compute the low and high output levels if (W=L)1 = 20=0:18 and RD = 5 k . Assume the input swings from zero to VDD.

4.Some IC technologies provide no high-quality resistors. We may thus replace the resistor in a CS stage with a MOS realization as shown in Fig. 15.39. Here, M2 approximates a pull-up resistor. Assume (W=L)1 = 3=0:18 and (W=L)2 = 2=0:18.

VDD

M 2

Vout

VinM 1

Figure 15.39

(a)Suppose Vin = VDD. Assuming M2 is in saturation, calculate the output low level. Is this assumption valid?

(b)Determine the trip point of this inverter, i.e., the input level at which Vout = Vin.

5.In the inverter of Fig. 15.39, the output low level must remain below 100 mV. If (W=L)2 = 3=0:18, determine the minimum required value of (W=L)1.

6.The inverter of Fig. 15.39 must provide an output low level no higher than 80 mV. If (W=L)1 = 2=0:18, what is the maximum allowable value of (W=L)2?

7.Due to a manufacturing error, an NMOS inverter has been reconfigured as shown in Fig. 15.40.