Fundamentals of Microelectronics

Gain

1

Vin

Figure 13.7 Gain of push-pull stage as a function of input.

Exercise

Repeat the above example if RL is replaced with an ideal current source.

In summary, the simple push-pull stage of Fig. 13.3(a) operates as a pnp or npn emitter follower for sufficiently negative or positive inputs, respectively, but turns off for ,600 mV < Vin < +600 mV. The resulting dead zone substantially distorts the input signal.

Example 13.4

Suppose we apply a sinusoid with a peak amplitude of 4 V to the push-pull stage of Fig. 13.3(a). Sketch the output waveform.

Solution

For Vin well above 600 mV, either Q1 or Q2 serves as an emitter follower, thus producing a reasonable sinusoid at the output. Under this condition, the plot in Fig. 13.5 indicates that Vout = Vin + jVBE2j or Vin , VBE1. Within the dead zone, however, Vout 0. Illustrated in Fig. 13.8, Vout exhibits distorted “zero crossings.” We also say the circuit suffers from “crossover

t

−0.6 V

Figure 13.8 Input and output waveforms in the presence of dead zone.

distortion.”

Exercise

Sketch the input and output waveforms if the push-pull stage incorporates NMOS and PMOS

transistors with zero threshold voltage.

13.4 Improved Push-Pull Stage

13.4.1 Reduction of Crossover Distortion

In most applications, the distortion introduced by the simple push-pull stage of Fig. 13.3(a) proves unacceptable. We must therefore devise methods of reducing or eliminating the dead zone.

The distortion in the push-pull stage fundamentally arises from the input connections: since the bases of Q1 and Q2 in Fig. 13.3(a) are shorted together, the two transistors cannot remain on simultaneously around Vin = 0. We surmise that the circuit can be modified as shown in Fig. 13.9(a), where a battery of voltage VB is inserted between the two bases. What is the required

Figure 13.9 (a) Addition of voltage source to remove the dead zone, (b) input and output waveforms, (c) input/output characteristic.

value of VB? If Q1 is to remain on, then V1 = Vout + VBE1. Similarly, if Q2 then V2 = Vout , jVBE2j. Thus,

VB = V1 , V2

= VBE1 + jVBE2j:

We say VB must be approximately equal to 2VBE (even though VBE1 and jVBE2j may not be equal).

With the connection of Vin to the base of Q2, Vout = Vin +jVBE2j; i.e., the output is a replica of the input but shifted up by jVBE2j. If the base-emitter voltages of Q1 and Q2 are assumed constant, both transistors remain on for all input and output levels, yielding the waveforms depicted in Fig. 13.9(b). The dead zone is thus eliminated. The input/output characteristic is illustrated in Fig. 13.9(c).

Example 13.5

Study the behavior of the stage shown in Fig. 13.10(a). Assume VB 2VBE.

Solution

In this circuit, both transistors remain on simultaneously, and Vout = Vin , VBE1. Thus, the

Figure 13.10 (a) Push-pull stage with input applied to base of Q1, (b) input and output waveforms, (c) input/output characteristic.

output is a replica of the input but shifted down. Figures 13.10(b) and (c) plot the waveforms and the input/output characteristic, respectively.

Exercise

What happens if VB VBE?

We now determine how the battery VB in Fig. 13.9(a) must be implemented. Since VB = VBE1 + jVBE2j, we naturally decide that two diodes placed in series can provide the required voltage drop, thereby arriving at the topology shown in Fig. 13.11(a). Unfortunately, the diodes carry no current here (why?), exhibiting a zero voltage drop. This difficulty is readily overcome

by adding a current source on top [Fig. 13.11(b)]. Now, I1 provides both the bias current of D1 and D2 and the base current of Q1.

Example 13.6

Determine the current flowing through the voltage source Vin in Fig. 13.11(b).

Solution

The current flowing through D1 and D2 is equal to I1 , IB1 (Fig. 13.12). The voltage source

694 Chap. 13 Output Stages and Power Amplifiers

must sink both this current and the base current of Q2. Thus, the total current flowing through

Figure 13.12 Circuit to examine base currents.

this source is equal to I1 , IB1 + jIB2j.

Exercise

Sketch the current flowing through the voltage source as a function of Vin as Vin goes from ,4 V to +4 V. Assume 1 = 25; 2 = 15, and RL = 8 .

Example 13.7

Under what condition are the base currents of Q1 and Q2 in Fig. 13.11(b) equal? Assume

1 = 2 1.

Solution

We must seek the condition IC1 = jIC2j. As depicted in Fig. 13.13, this means no current flows through RL and Vout = 0. As Vout departs from zero, the current flowing through RL is provided

VEE

Figure 13.13 Stage with zero output voltage.

by either Q1 or Q2 and hence IC1 =6 jIC2j and IB1 =6 jIB2j. Thus, the base currents are equal only at Vout = 0.

Exercise

Repeat the above example if 1 = 2 2.

Example 13.8

Study the behavior of the circuit illustrated in Fig. 13.14, where I2 absorbs both the bias current

I 2

VEE

Figure 13.14 Stage with input applied to midpoint of diodes.

of D2 and IB2.

Solution

Here, we have V1 = Vin + VD1 and Vout = V1 , VBE1. If VD1 VBE1, then Vout Vin, exhibiting no level shift with respect to the input. Also, the current flowing through D1 is equal to I1 , IB1 and that through D2 equal to I2 , jIB2j. Thus, if I1 = I2 and IB1 IB2, the input voltage source need not sink or source a current for Vout = 0, a point of contrast with respect to the circuit of Fig. 13.12.

Exercise

Sketch the current provided by the input source as a function of Vin as Vin goes from ,4 V to +4 V. Assume 1 = 25; 2 = 15, and RL = 8 .

13.4.2 Addition of CE Stage

The two current sources in Fig. 13.14 can be realized with pnp and npn transistors as depicted in Fig. 13.15(a). We may therefore decide to apply the input signal to the base of one of the current sources so as to obtain a greater gain. Illustrated in Fig. 13.15(b), the idea is to employ Q4 as a common-emitter stage, thus providing voltage gain from Vin to the base of Q1 and Q2.3 The CE stage is called the “predriver.”

The push-pull circuit of Fig. 13.15(b) is used extensively in high-power output stages and merits a detailed analysis. We must first answer the following questions: (1) Given the bias currents of Q3 and Q4, how do we determine those of Q1 and Q2? (2) What is the overall voltage gain of the circuit in the presence of a load resistance RL?

To answer the first question, we assume Vout = 0 for bias calculations and also IC4 = IC3. If VD1 = VBE1 and VD2 = jVBE2j, then VA = 0 (why?). With both Vout and VA at zero, the

3If the dc level of Vin is close to VCC, then Vin is applied to the base of Q3 instead.

Figure 13.15 (a) Push-pull stage with realization of current sources, (b) stage with input applied to base of Q4.

circuit can be reduced to that shown in Fig. 13.16(a), revealing a striking resemblance to a current

Figure 13.16 (a) Simplified diagram of a push-pull stage, (b) illustration of current mirror action.

mirror. In fact, since

where the base current of Q1 is neglected and IS;D1 denotes the saturation current of D1, and since VBE1 = VT ln(IC1 =IS;Q1), we have

To establish a well-defined value for IS;Q1=IS;D1, diode D1 is typically realized as a diodeconnected bipolar transistor [Fig. 13.16(b)] in integrated circuits. Note a similar analysis can be applied to the bottom half of the circuit, namely, Q4, D2, and Q2.

The second question can be answered with the aid of the simplified circuit shown in Fig. 13.17(a), where VA = 1 and 2rD represents the total small-signal resistance of D1 and D2. Let us assume for simplicity that 2rD is relatively small and v1 v2, further reducing the circuit to

Figure 13.17 (a) Simplified circuit to calculate gain, (b) circuit with resistance of diodes neglected, (c) small-signal model.

that illustrated in Fig. 13.17(b),4 where

Now, Q1 and Q2 operate as two emitter followers in parallel, i.e., as a single transistor having an r equal to r 1jjr 2 and a gm equal to gm1 + gm2 [Fig. 13.17(c)]. For this circuit, we have

v 1 = vpi2 = vN , vout and

Multiplying the numerator and denominator by RL, dividing both by 1+(gm1 +gm2)(r 1jjr 2), and assuming 1 + (gm1 + gm2)(r 1jjr 2) 1, we obtain

4It is important to note that this representation is valid for signals but not for biasing.

698 Chap. 13 Output Stages and Power Amplifiers

(Note that for IC1 = IC2 and 1 = 2, this expression reduces to the input impedance of a simple emitter follower.) Consequently,

Example 13.9

Calculate the output impedance of the circuit shown in Fig. 13.18(a). For simplicity, assume

(d)

Figure 13.18 (a) Circuit for calculation of output impedance, (b) simplified diagram, (c) further simplification, (d) small-signal model.

2rD is small.

Solution

The circuit can be reduced to that in Fig. 13.18(b), and, with 2rD negligible, to that in Fig. 13.18(c). Utilizing the composite model illustrated in Fig. 13.17(c), we obtain the small-signal equivalent circuit of Fig. 13.18(d), where VA = 1 for Q1 and Q2 but not for Q3 and Q4. Here, rO3jjrO4 and rpi1jjrpi2 act as a voltage divider:

The key observation here is that the second term in (13.27) may raise the output impedance considerably. As a rough approximation, we assume rO3 rO4, gm1 gm2, and r 1 r 2, concluding that the second term is on the order of (rO=2)= . This effect becomes particularly problematic in discrete design because power transistors typically suffer from a low .

Exercise

If rO3 rO4, gm1 gm2, and r 1 r 2, for what value of is the second term in (13.27) equal to the first?

13.5 Large-Signal Considerations

The calculations in Section 13.4.2 reveal the small-signal properties of the improved push-pull stage, providing a basic understanding of the circuit's limitations. For large-signal operation, however, a number of other critical issues arise that merit a detailed study.

13.5.1 Biasing Issues

We begin with an example.

Example 13.10

We wish to design the output stage of Fig. 13.15(b) such that the CE amplifier provides a voltage gain of 5 and the output stage, a voltage gain of 0.8 with RL = 8 . If npn = 2 pnp = 100 and VA = 1, compute the required bias currents. Assume IC1 IC2 (which may not hold for large signals).

Solution

Exercise

Repeat the above example if the second stage must provide a voltage gain of 2.

The above example entails moderate current levels in the milliampere range. But what happens if the stage must deliver a swing of, say, 4 VP to the load? Each output transistor must now provide a peak current of 4 V=8 = 500 mA. Does the design in Example 13.10 deliver such voltage and current swings without difficulty? Two issues must be considered here. First, a bipolar transistor carrying 500 mA requires a large emitter area, about 500 times the emitter area of a transistor capable of handling 1 mA.5 Second, with a of 100, the peak base current reaches as high as 5 mA! How is this base current provided? Transistor Q1 receives maximum base current if Q4 turns off so that the entire IC3 flows to the base of Q1. Referring to the bias currents obtained in Example 13.10, we observe that the circuit can be simplified as shown in Fig. 13.19 for the peak of positive half cycles. With an IC3 of only 195 A, the collector current

VCC

Vb1 Q 3

195 A Q 1

D1

Vout

D2

RL

Q 2

VinQ 4

VEE

Figure 13.19 Calculation of maximum available current.

of Q1 cannot exceed roughly 100 195 A = 19:5 mA, far below the desired value of 500 mA. The key conclusion here is that, while achieving a small-signal gain of near unity with an 8- load, the output stage can deliver an output swing of only 195 mA 8 = 156 mVP . We must therefore provide a much higher base current, requiring proportionally higher bias currents in the predriver stage. In practice, power transistors suffer from a low , e.g., 20, exacerbating this

issue.

13.5.2 Omission of PNP Power Transistor

PNP power transistors typically suffer from both a low current gain and a low fT , posing serious constraints on the design of output stages. Fortunately, it is possible to combine an npn device with a pnp transistor to improve the performance.

Consider the common-emitter npn transistor, Q2, depicted in Fig. 13.20(a). We wish to modify the circuit such that Q2 exhibits the characteristics of an emitter follower. To this end, we add the pnp device Q3 as shown in Fig. 13.20(b) and prove that the Q2-Q3 combination operates as an emitter follower. With the aid of the small-signal equivalent circuit illustrated in Fig. 13.20(c) (VA = 1), and noting that the collector current of Q3 serves as the base current of Q2, and hence gm2v 2 = , 2gm3(vin , vout), we write a KCL at the output node:

5For a given emitter area, if the collector current exceeds a certain level, “high-level injection” occurs, degrading the transistor performance, e.g., .