Fundamentals of Microelectronics

16.With the aid of the observations made for Eq. (14.25), determine a condition for the low-pass filter of Fig. 14.29 to exhibit a peaking of 1 dB ( 10%).

17.Determine the poles of the Sallen and Key filter shown in Fig. 14.33 and plot their location in the complex plane as (a) R1 varies from zero to 1, (b) R2 varies from zero to 1, (c)

C1 varies from zero to 1, or (d) C2 varies from zero to 1. In each case, assume other component values remain constant.

18.A student mistakenly configures a Sallen and Key filter as shown in Fig. 14.60. Determine the transfer function and explain why this is not a useful circuit.

Figure 14.60

19. The Sallen and Key filter of Fig. 14.34 must be designed with K = 4 and C1 = C2. How should R1=R2 be chosen to yield Q = 4? What is the resulting Q sensitivity to R1?

20. A Sallen and Key filter with K = 1 must exhibit a peaking of only 1 dB in its response. Determine the relationship required among the component values.

21. The Sallen and Key filter of Fig. 14.33 exhibits SQ = 2. If C2 = C1, plot Q as a function

R1

of pR2=R1 and determine the acceptable range of values of Q and pR2=R1.

22.Figure 14.61 shows a high-pass Sallen and Key filter. Derive the transfer function and determine Q and !n.

Figure 14.61

23.From the results obtained in Problem 22, compute the Q sensitivities of the circuit.

24.It is possible to realize the transfer function of Eq. (14.95) by means of differentiators rather than integrators. Noting that the factor s in the frequency domain translates to d=dt in the time domain, construct a block diagram such as that shown in Fig. 14.36(a) but using only differentiators. (Due to amplification of noise at high frequencies, this implementation is less popular.)

25.The KHN biquad of Fig. 14.36(b) must provide a band-pass response with Q = 2 and

!n = 2 (2 MHz). Fig. R6 = R3, R1 = R2, and C1 = C2, determine the resistor and capacitor values subject to the restrictions 10 pF< C < 1 nF and 1 k < R < 50 k .

26.From Eqs. (14.103) and (14.104), derive an expression for Q and explain why the sensitivity to R3 and R6 vanishes if R3 = R6.

27.The KHN biquad of Fig. 14.36(b) must be designed for a low-pass response with a low-

28.A KHN biquad must exhibit a peaking of only 1 dB in its low-pass response. Determine the relationship required among the component values. Assume R3 = R6 and the gain is unity.

29.A student mistakenly omits resistor R5 from the KHN biquad of Fig. 14.36(b). Derive the resulting transfer function Vout=Vin and determine , Q, and !n.

30.Determine the sensitivities of the Tow-Thomas filter shown in Fig. 14.37 with respect to resistor and capacitor values.

31.Equation (14.114) implies that the low-frequency gain of the Tow-Thomas filter is equal to

R4=R1. Setting C1 and C2 to zero in Fig. 14.37, explain intuitively why this result makes sense.

32.The Tow-Thomas filter of Fig. 14.37 must be designed for a low-pass response having a peaking of 1 dB and a bandwidth !n = 2 (10 MHz). If R3 = 1 k , R2 = R4, and C1 = C2, determine the values of R2 and C1.

33.The transfer function in (14.114) reveals that resistor R1 affects the low-frequency gain of the Tow-Thomas filter but not the frequency response. Replacing Vin and R1 in Fig. 14.37 with a Norton equivalent, explain intuitively why this result makes sense.

34.For the general impedance converter of Fig. 14.39, determine all possible combinations of

Z1-Z5 that yield an inductive behavior for Zin. Assume each of Z1-Z5 consists of only one resistor or one capacitor. (Note that a solution is not acceptable if it does not provide a dc path to each input of the op amps.)

35.Repeat Problem 34 if a capacitive behavior for Zin is required.

36.In Example 14.23, the parallel RC branch tied between node 5 and ground is replaced with a series branch RX + (Cs),1. Determine the resulting transfer function Vout=Vin.

37.Select the components in Fig. 14.39 such that the circuit provides a large capacitive impedance, i.e., it multiplies the value of a capacitor by a large number.

38.We wish to design a Butterworth filter with a roll-off of 1 dB at ! = 0:9!0. Determine the required order.

39.Using Eq. (14.138), plot the roll-off of a Butterworth response at ! = 0:9!0 as a function of n. Express the roll-off (on the vertical axis) in decibels.

40.Repeat Problem 39 for ! = 1:1!0. What order is required to obtain an attenuation of 20 dB at this frequency?

41.Suppose the filter of Example 14.24 receives an interferer at 5 MHz. How much attenuation does the filter provide?

42. A low-pass Butterworth filter must provide a passband flatness of 0.5 dB for f < f1 = 1 MHz. If the order of the filter must not exceed 5, what is the greatest stopband attenuation at f2 = 2 MHz?

43.Explain why the poles expressed by Eq. (14.148) lie on a circle.

44.Repeat Example 14.25 but with an KHN biquad.

45.Repeat Example 14.25 but with a Tow-Thomas filter.

46.Plot the Chebyshev response expressed by Eq. (14.159) for n = 4 and = 0:2. Estimate the locations of the local maxima and minima in the passband.

47.A Chebyshev filter must provide an attenuation of 25 dB at 5 MHz. If the order of the filter must not exceed 5, what is the minimum ripple that can be achieved across a bandwidth of 2 MHz?

48.Repeat Problem 47 for an order of 6 and compare the results.

49.Repeat Example 14.28 but with two KHN biquads.

50. Repeat Example 14.28 but with two Tow-Thomas biquads.

Design Problems

51.Design the first-order filter of Fig. 14.18(a) for a high-pass response so that the circuit attenuates an interferer at 1 MHz by 10 dB and passes frequencies above 5 MHz with a gain close to unity.

52.Design the passive filter of Fig. 14.29 for a ,3-dB bandwidth of approximately 100 MHz, a peaking of 1 dB, and an inductance value less than 100 nH.

53.Design the SK filter of Fig. 14.33 for !n = 2 (50 MHz), Q = 1:5, and low-frequency gain of 2. Assume capacitor values must fall in the range of 10 pF to 100 pF.

54.Design a low-pass SK filter for a ,3-dB bandwidth of 30 MHz with sensitivities no greater than unity. Assume a low-frequency gain of 2.

55.Design the KHN biquad of Fig. 14.36(b) for a bandpass response so that it provides a peak gain of unity at 10 MHz and an attenuation of 13 dB at 3 MHz and 33 MHz. Assume

R3 = R6.

56.The design obtained in Problem 55 also provides low-pass and high-pass outputs. Determine the ,3-dB corner frequencies for these two transfer functions.

57.Repeat Problem 55 for the Tow-Thomas biquad shown in Fig. 14.37.

58.Design the active high-pass filter of Fig. 14.42 for a ,3-dB corner frequency of 3.69 MHz and an attenuation of 13.6 dB at 2 MHz. Assume a peaking of 1 dB at 7 MHz.

59.Design the low-pass filter of Fig. 14.44(b) for a ,3-dB bandwidth of 16.4 MHz and an attenuation of 6 dB at 20 MHz. Assume a peaking of 0.5 dB at 8 MHz.

60.For each frequency response template shown in Fig. 14.62, determine a Butterworth and a Chebyshev transfer function.

Figure 14.62

61. Following the methodology outlined in Examples 14.25 and 14.28, design filters for the Butterworth and Chebyshev transfer functions obtained in Problem 14.62.

62. Repeat Problem 61 but with Tow-Thomas biquads (and, if necessary, first-order RC sections).

SPICE Problems

63. Figure 14.63 shows the Butterworth filter designed in Example 14.25.

228 pF

Figure 14.63

(a)Simulate the circuit with an op amp gain of 500 and determine if it meets the template specified in Example 14.24.

(b)Repeat (a) if the op amp exhibits an (open-loop) output resistance of 10 k . (The output resistance can be modeled by inserting a 10-k in series with the voltage-dependent source.)

(c)Repeat (b) if the op amp exhibits a single (open-loop) pole at 500 kHz. (The pole can be modeled by allowing a capacitor to form a low-pass filter with the 10-k resistor.)

64.Repeat Problem 63 for the design obtained in Example 14.28.

65.(a) Repeat Example 14.28 with a cascade of two KHN biquads.

(b)Using SPICE, determine the minimum required op amp bandwidth if the overall response must exhibit a peaking no higher than 3 dB. Assume an op amp gain of 1000 and model the bandwidth as explained in Problem 63.

(c)Repeat (b) for the SK realization obtained in Example 14.28 and compare the results.

66.We must select an op amp for the SK design in Example 14.25. Suppose two types of op amps are available: one with an output resistance of 5 k and a single pole at 200 MHz, and another with an output resistance of 10 k and single pole at 100 MHz. Use SPICE to determine which op amp yields smaller peaking.

67.Consider the SK design in Example 14.25. Suppose the op amp provides an open-loop gain of 1000 but is otherwise ideal.

(a)Does the response meet the template in Example 14.24 if all three resistor experience a change of +10%?

(b)Does the response meet the template in Example 14.24 if all three capacitors experience a change of +10%?

(c)What is the maximum tolerable error in the value of the resistors?

References

1. R. Schaumann and M. E. van Valkenberg, Design of Analog Filters, Oxford University Press, 2001.

Digital CMOS Circuits

It is virtually impossible to find electronic devices in our daily lives that do not contain digital circuits. From watches and cameras to computers and cellphones, digital circuits account for more than 80% of the semiconductor market. Examples include microprocessors, memories, and digital signal processing ICs.

This chapter serves as an introduction to the analysis and design of digital CMOS circuits. The objective is to provide a detailed transistor-level understanding of logical gates so as to prepare the reader for courses on digital circuit design. The outline is shown below.

15.1 General Considerations

In the past five decades, digital circuits have evolved dramatically, going from a few gates per chip in the 1960s to hundreds of millions of transistors per chip today. Very early generations incorporated only resistors and diodes and were called “resistor-diode logic” (RDL). These were followed by bipolar realizations such as “transistor-transistor logic” (TTL) and “emitter-coupled logic” (ECL). But it was the advent of CMOS technology and the unique properties of digital CMOS circuits that led to the explosive growth of digital systems. We will study and appreciate these properties in this chapter.

Recall from basic logic design that digital systems employ building blocks such as gates, latches, and flipflops. For example, gates can form a “combinational” circuit that operates as a binary-Gray decoder. Similarly, gates and flipflops can comprise a “sequential” circuit that serves as a counter or a “finite-state machine.” In this chapter, we delve into the internal design of some of these building blocks and analyze their limitations. In particular, we address three important questions:

(1)What limits the speed of a digital gate?

(2)How much power does a gate consume while running at a certain speed?

(3)How much “noise” can a gate tolerate while producing a valid output?

775

These questions play a critical role in the design of digital systems. The first reveals how microprocessor speeds have risen from a few hundred megahertz to several gigahertz in past ten years. The second helps predict how much power a microprocessor drains from the battery of a laptop computer. The third illustrates how reliably a gate operates in the presence of nonidealities in the system.

15.1.1 Static Characterization of Gates

Unlike many of the amplifying stages studied in this book, logical gates always operate with large signals. In digital CMOS circuits, a logical ONE is represented by a voltage equal to the supply, VDD, and a logical ZERO by zero volt. Thus, the inputs and outputs of gates swing between zero and VDD as different states are processed.

How do we characterize the large-signal behavior of a circuit? Recall from Chapter 3 that we can construct the input/output characteristic by varying the input across the entire allowable range (e.g., 0 to VDD) and computing the corresponding output. Also called the “voltage transfer characteristic” (VTC), 1 the result illustrates the operation of the gate in great detail, revealing departures from the ideal case.

As an example, consider a NOT gate whose logical operation is expressed as X = A. Called an “inverter” and denoted by the symbol shown in Fig. 15.1(a), such a gate must ideally behave

Figure 15.1 (a) Inverter, (b) ideal characteristic.

as depicted in Fig. 15.1(b). For Vin = 0, the output remains at a logical ONE, Vout = VDD. For Vin = VDD, the output provides a logical zero, Vout = 0. As Vin goes from 0 to VDD, Vout abruptly changes its state at some value of the input, V1.

Example 15.1

Explain why a common-source stage can operate as an inverter.

Solution

In the CS stage shown in Fig. 15.2(a), if Vin = 0, then M1 is off, the voltage drop across RD

Figure 15.2 (a) CS stage, (b) input/output characteristic.

is zero, and hence Vout = VDD. On the other hand, if Vin = VDD, M1 draws a relatively large

1The term “transfer” should not create confusion with the transfer function.

current from RD and Vout = VDD , IDRD can be near zero. Thus, as sketched in Fig. 15.2(b), the input/output characteristic resembles that of an inverter.

Exercise

What happens if RD is replaced by a PMOS current source?

Example 15.2

A common-source stage operates as a inverter. Determine the VTC for such a realization.

Solution

Consider the CS stage shown in Fig. 15.3(a). We vary Vin from 0 to VDD and plot the corre-

Figure 15.3 (a) CS stage, (b) equivalent circuit for M1 in deep triode region, (c) input/output characteristic.

sponding output. For Vin VTH, M1 remains off and Vout = VDD (logical ONE). As Vin exceeds VTH , M1 turns on and Vout begins to fall:

where channel-length modulation is neglected. As the input increases further, Vout drops, eventually driving M1 into the triode region for Vout Vin , VTH and hence:

From this equation, the value of Vin that places M1 at the edge of triode region can be calculated. As Vin exceeds this value, Vout continues to decrease, reaching its lowest level for Vin = VDD:

Equation (15.5) can be solved to obtain Vout;min. If we neglect the second term in the square brackets, then

[ nCox(W=L)RD(VDD , VTH )],1 and hence Vout;min a result of voltage division between RD and Ron1 [Fig. 15.3(b)]. Figure 15.3(c) plots the VTC, illustrating the regions of operation. In this role, the CS stage is also called an “NMOS inverter.”

Exercise

Repeat the above example if RD is replaced with a PMOS current source.

Can the characteristic of Fig. 15.1(b) be realized in practice? We recognize that Vout changes by an amount equal to VDD for an infinitesimally small change in Vin around V1, i.e., the voltage gain of the circuit is infinite at this point. In reality, as illustrated in Example 15.2, the gain remains finite, thereby producing a gradual transition from high to low (Fig. 15.4). We may call

Vout

VDD

Figure 15.4 Characteristic with finite gain.

the range V0 < Vin < V2 the “transition region.”

Example 15.3

An inverter must exhibit a transition region only 50 mV wide. If the supply voltage is 1.8 V, estimate the gain of the circuit in this region.

Solution

Since a 50-mV change at the input results in a change of approximately 1.8 V at the output, the voltage gain is equal to 1:8=0:05 = 36.

Exercise

What happens to the transition region if the width of the NMOS transistor is increased?

The reader may wonder why the gradual transition in Fig. 15.4 may prove problematic. After all, if the input jumps between 0 and VDD, the output still provides valid logical levels. In reality, however, the input may not reach exactly 0 or VDD. For example, a logical zero may appear as +100 mV rather than 0 V. Such “degradation” of the logical levels arises from a multitude of phenomena in a large integrated circuit, but a simple example can illustrate this effect.

Example 15.4

The supply voltage, VDD, is distributed on a microprocessor chip through a wide metal line 15 mm long [Fig. 15.5(a)]. Called the “power bus,” this line carries a current of 5 A and suffers

(b)

Figure 15.5 (a) Two inverters separated by a long distance on a chip, (b) equivalent supply voltages.

from a resistance of 25 m . If inverter Inv1 produces a logical ONE given by the local value of VDD, determine the degradation in this level as sensed by inverter Inv2.

Solution

The power bus experiences a voltage drop of 5 A 25 m = 125 mV from point A to point B, thereby allowing a logical ONE of only 1:8 V , 0:125 V = 1:675 V at the output of Inv1 [Fig. 15.5(b)]. As a result, Inv2 senses a high level that is degraded by 125 mV with respect to its own supply voltage, 1.8 V.

Exercise

Repeat the above example if the width of the power bus is halved.

How much degradation can we tolerate in the input levels applied to a gate? Consider the situation depicted in Fig. 15.6, where both the low and high levels of the input, V0 and V2,

Figure 15.6 Degradation of output levels in an inverter.

respectively, depart considerably from their ideal values. Mapping these levels to the output,

we observe that Vout also exhibits degraded logical levels. In a chain of gates, such successive degradations may make the system very “fragile” and even completely corrupt the states.

Example 15.5

Sketch the small-signal voltage gain for the characteristic shown in Fig. 15.4 as a function of

Vin.

Solution

The slope of the VTC begins from zero, becomes more negative above V0, and approaches zero again for Vin > V2. Figure 15.7 plots the result.

dVout

dV in

Figure 15.7

Exercise

Is this plot necessarily symmetric? Use an CS stage as an example.

Example 15.6

Prove that the magnitude of the small-signal gain obtained in Example 15.5 must exceed unity at some point.

Solution

Superimposing a line with a slope of ,1 on the VTC as shown in Fig. 15.8, we note that the

Vout

VDD

−1

VDD Vin

Figure 15.8

slope of the VTC is sharper than unity across part of the transition region. This is because the transition region spans a range narrower than 0 to VDD.

Exercise

An inverter exhibits a gain of about 2 in its transition region. How wide is the transition