Fundamentals of Microelectronics

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Noise Margin In order to quantify the robustness of a gate with respect to the degradation of the input logical levels, we introduce the concept of “noise margin” (NM). A rough definition is: NM is the maximum amount of degradation (noise) at the input that can be tolerated before the output is affected “significantly.” What do we mean by “significantly?” We postulate that the output remains relatively unaffected if the gain of the circuit remains below unity, thus arriving at the following definition:

The noise margin is the maximum departure from the ideal logical level that places the gate at a small-signal voltage gain of unity.

The procedure for calculating NM is straightforward: we construct the VTC and determine the input level at which the small-signal gain reaches unity. The difference between this level and the ideal logical level yields the NM. Of course, we associate a noise margin with the input low level, NML, and another with the input high level, NMH. Figure 15.9 summarizes these

Vout

VDD

Figure 15.9 Illustration of noise margins.

concepts. The two input voltages are denoted by VIL and VIH, respectively.

Example 15.7

A common-source stage operates as an NMOS inverter. Compute the noise margins.

Solution

We can adopt one of two approaches here. First, since the small-signal gain of the stage is equal to ,gmRD and since gm = nCox(W=L)(VGS , VTH ), we have

In the second approach, we directly differentiate both sides of Eq. (15.2) with respect to Vin:

That is, the input must exceed VTH by ( nCoxRDW=L),1 for the circuit to reach the unity-gain point.

As Vin drives M1 into the triode region, the transconductance of M1 and hence the voltage gain of the circuit begin to fall. Since in Chapter 6, we did not derive a small-signal model for MOSFETs operating in the triode region, we continue with the second approach:

We must equate the slope of this characteristic to ,1 to determine NMH:

If this value of Vout is substituted in (15.13), the required value of Vin (VIH in Fig. 15.9) can be obtained. Thus, NMH = VDD , VIH .

Exercise

If RD = 1 k ; nCox = 100 A/V2; W=L = 10; VTH = 0:5 V, and VDD = 1:8 V, calculate the high and low noise margins.

Example 15.8

As suggested by (15.6), the output low level of an NMOS inverter is always degraded. Derive a relationship to guarantee that this degradation remains below 0:05VDD.

Solution

Note that the right hand side is equal to 19 times the on-resistance of M1. Thus, RD must remain above 19Ron1.

Exercise

Repeat the above example if the degradation can be as high as 0.1VDD.

15.1.2 Dynamic Characterization of Gates

The input/output characteristic of a gate proves useful in determining the degradations that the circuit can tolerate in its input levels. Another important aspect of a gate's performance is its speed. How do we quantify the speed of a logical gate? Since the gate operates with large signals at the input and output and hence experiences heavy nonlinearity, the concepts of transfer function and bandwidth are not meaningful here. Instead, we must define the speed according to the role of gates in digital systems. An example serves us well at this point.

Example 15.9

The input to an NMOS inverter jumps from VDD to 0 at t = 0 [Fig. 15.10(a)]. If the circuit sees

Figure 15.10 (a) NMOS inverter experiencing a step input, (b) charging path for CL, (c) input and output waveforms.

a load capacitance of CL, how long does the output take to reach within 5% of the ideal high level? Assume Vout can be approximated by (15.6) when M1 is on.

Solution

At t = 0,, M1 is on, establishing an initial condition across CL equal to

At t = 0+, the circuit reduces to that shown in Fig. 15.10(b), where CL charges toward VDD through RD. We therefore have

(This equation is constructed such that the first term denotes the initial value if we choose t = 0, and the sum of the first and second terms yields the final value if we select t = 1.) The time

In other words, the output takes about three time constants to reach a voltage close to the ideal high level [Fig. 15.10(c)]. Unlike ideal gates used in basic logic design, this inverter exhibits a finite transition time at the output.

Exercise

How many time constants does the output take to reach within 90% of its ideal value.

The foregoing example reveals a fundamental limitation: in the presence of a load capacitance, a logical gate cannot respond immediately to an input. The circuit of Fig. 15.10(a) takes roughly three time constants to produce a reliable level at the output and, as such, suffers from a “delay.” That is, the speed of gates is limited by the finite transition time at the output and the resulting delay.

Playing a critical role in high-speed digital design, the transition time and the delay must be defined carefully. As illustrated in Fig. 15.11(a), we define the output “risetime,” TR, as the time

Figure 15.11 Definition of (a) rise and fall times, and (b) propagation delays.

required for the output to go from 10% of VDD to 90% of VDD.2 Similarly, the output “falltime,”

Sec. 15.1 General Considerations 785

TF , is defined as the time required for the output to go from 90% of VDD general, TR and TF may not be equal.

Since the input to a gate is produced by another gate and hence suffers from a finite transition time, the delay of the gate must be characterized with a realistic input waveform rather than the abrupt step in Fig. 15.11(a). We therefore apply a step with a typical risetime at the input and define the propagation delay as the difference between the time points at which the input and the output cross VDD=2 [Fig. 15.11(b)]. Since the output rise and fall times may not be equal, a low-to-high delay, TPLH, and a high-to-low delay, TPHL, are necessary to characterize the speed. In today's CMOS technology, gate delays as little as 10 ps can be obtained.

The reader may wonder about the nature of the load capacitance in Example 15.9. If the gate drives only another stage on the chip, this capacitance arises from two sources: the input capacitance of the subsequent gate(s) and the capacitance associated with the “interconnect” (on-chip wire) that carries the signal from one circuit to another.

Example 15.10

An NMOS inverter drives an identical stage as depicted in Fig. 15.12. We say the first gate sees a

“fanout” of unity. Assuming a 5% degradation in the output low level (Example 15.8), determine the time constant at node X when VX goes from low to high. Assume CX W LCox.

Solution

Recall from Example 15.9 that this time constant is simply equal to RDCX. Assuming RD = 19Ron1, we write

Exercise

Suppose the width of M2 is doubled while M1 remains unchanged. Calculate the time constant.

Example 15.11

In Example 15.4, the wire connecting the output of Inv1 to the input of Inv2 exhibits a ca-

pacitance of 50 10,18 F (50 aF)3 per micron of length. What is the interconnect capacitance driven by Inv1?

Solution

For 15,000 microns, we have

To appreciate the significance of this value, let us calculate the gate capacitance of a small MOSFET, e.g., with W = 0:5 m, L = 0:18 m, and Cox = 13:5 fF= m2:

In other words, Inv1 sees a load equivalent to a fanout of 750 fF=1:17 fF 640; as if it drives 640 gates.

Exercise

What is the equivalent fanout if the width of the wire is halved?

15.1.3 Power-Speed Trade-Off

Integrated circuits containing millions of gates can consume a very high power (tens of watts). The power dissipation proves critical for several reasons. First, it determines the battery lifetime in portable applications such as laptop computers and cellphones. Second, it tends to raise the temperature of the chip, degrading the performance of the transistor.4 Third, it requires special (expensive) packages that can conduct the heat away from the chip.

How does a gate consume power? Let us consider the NMOS inverter of Fig. 15.13 as an

VDD

R D

X Vout

Figure 15.13 NMOS inverter driving a load capacitance.

example. If Vin = 0, M1 is off. On the other hand, if Vin = VDD, M1 draws a current equal to

3The abbreviation for 10 18 is called “ato.”

4For example, the mobility of MOS devices falls as the temperature rises.

Sec. 15.1 General Considerations 787

which, from (15.6), translates to

The gate thus consumes a power of ID VDD while the output is low. (If RD Ron1, then

determined by the time constant RDCL. We therefore observe a direct trade-off between the power dissipation and the speed: a high value of RD reduces the power dissipation but yields a longer delay. In fact, we may define a figure of merit as the product of the power dissipation and the time constant:

In digital design, the figure of merit is defined as the product of the power dissipation, P, and the gate delay rather than the output time constant. This is because the nonlinear operation of gates often prohibits the use of a single time constant to express the output transition behavior.

Note that PDP has dimension of energy, i.e., it indicates how much energy is consumed for a logical operation.

Example 15.12

Consider the cascade of identical NMOS inverters studied in Example 15.10. Assuming TPLH is roughly equal to three time constants, determine the power-delay product for the low-to-high transitions at node X.

Solution

For example, if VDD = 1:8 V, W = 0:5 m, L = 0:18 m, and Cox = 13 fF= m2, then

P DP = 1:14 10,14 J = 11:4 fJ.

Exercise

How much average power is consumed if the circuit runs at a frequency of 1 GHz.

15.2 CMOS Inverter

Perhaps the most elegant and the most important circuit invention in CMOS technology, the CMOS inverter forms the foundation for modern digital VLSI systems. In this section, we study the static and dynamic properties of this circuit.

15.2.1 Initial Thoughts

We have seen in Section 15.1.1 that the NOT (inverter) function can be realized by a commonsource stage, Fig. 15.3(a). As formulated in Examples 15.8 and 15.9, this circuit faces the following issues: (1) the load resistance, RD, must be chosen much greater than the on-resistance of the transistor; (2) the value of RD creates a trade-off between speed and power dissipation;

(3) the inverter consumes a power of roughly V 2 =RD so long as the output remains low. Of

DD

particular concern in large digital circuits is the last effect, called “static power dissipation” because the inverter consumes energy even though it is not switching. For example, in a VLSI chip containing one million gates, half of the outputs may be low at a given point in time, thereby

demanding a power dissipation of 5 105 V 2 =RD. If VDD = 1:8 V and RD = 10 k , this

DD

amounts to 162 W of static power consumption!

The foregoing drawbacks of the NMOS inverter fundamentally arise from the “passive” nature of the load resistor, called the “pull-up” device here. Since RD presents a constant resistance between VDD and the output node, (1) M1 must “fight” RD while establishing a low level at the output and hence Ron1 must remain much smaller than RD [Fig. 15.14(a)]; (2) after M1 turns

Figure 15.14 (a) Degradation of output level in an NMOS inverter, (b) risetime limitation due to RD, (c) static power consumed during output low level.

off, only RD can pull the output node up toward VDD [Fig. 15.14(b)]; (3) the circuit draws a current of approximately VDD=RD from the supply when the output is low [Fig. 15.14(c)]. We therefore seek a more efficient realization that employs an “intelligent” pull-up device.

Let us ask, how should the ideal pull-up device behave in an inverter? When M1 turns off, the pull-up device must connect the output node to VDD, preferably with a low resistance [Fig. 15.15(a)]. On the other hand, when M2 turns on, the pull-up device must turn off so that no current can flow from VDD to ground (and Vout is exactly equal to zero). This latter property also reduces the falltime at the output, as illustrated in the following example.

Figure 15.15 Use of active pullup device for (a) high output and (b) low output. .

Example 15.13

Consider the two inverter implementations depicted in Fig. 15.16. Suppose Vin jumps from 0 to

Figure 15.16 Comparison of (a) NMOS inverter and (b) inverter using an active pull-up device.

VDD at t = 0 and the pull-up device in Fig. 15.16(b) turns off at the same time. Compare the output falltimes of the two circuits if M1 and CL are identical in the two cases.

Solution

In Fig. 15.16(a), M1 must absorb two currents: one carried by RD and another required to discharge CL. In Fig. 15.16(b), on the other hand, ID1 simply discharges CL because the pull-up device is turned off. As a consequence, Vout falls more rapidly in the topology of Fig. 15.16(b).

Exercise

For each circuit, determine the energy consumed by M1 as Vout falls from VDD to zero.

In summary, we wish the pull-up device in Fig. 15.15 to turn on when M1 turns off and vice versa. Is it possible to employ a transistor for this purpose and turn it on and off by the input voltage [Fig. 15.17(a)]? We recognized that the transistor must turn on when Vin is low, postulating that a PMOS device is necessary [Fig. 15.17(b)]. Called the “CMOS inverter,” this topology benefits from “cooperation” between the NMOS device and the PMOS device: when M1 wishes to pull Vout low, M2 turns off, and vice versa.

It is important to note that, by virtue of the “active” pull-up device, the CMOS inverter indeed avoids the drawbacks of the NMOS implementation: (1) the output low level is exactly equal to zero because Vin = VDD ensures that M2 remains off; (2) the circuit consumes zero static power for both high and low output levels. Figure 15.17(c) shows a rough sketch of the input/output characteristic, emphasizing that Vout = 0 for Vin = VDD. Throughout this chapter, we denote

Figure 15.17 (a) Pull-up device controlled by input, (b) CMOS inverter.

the aspect ratios of the NMOS and PMOS transistors in an inverter by (W=L)1 and (W=L)2, respectively.

15.2.2 Voltage Transfer Characteristic

We begin our in-depth study of the CMOS inverter with its static characteristics. We must vary Vin from zero to VDD and plot the corresponding output voltage. Note that the two transistors carry equal currents under all conditions (so long as the inverter is not loaded by any other circuit). Suppose Vin = 0 [Fig. 15.18(a)]. Then, M1 is off and M2 is on. How can M2 remain on

M 2

M 1

Figure 15.18 (a) CMOS inverter sensing a low input, (b) equivalent circuit, (c) supply current when both transistors are one, (d) small-signal model.

while jID2j = ID1 = 0? This is possible only if M2 sustains a zero drain-source voltage. That is,