Fundamentals of Microelectronics

VCC

Q 1

Device

Q 1 Vb

R F

I in

Figure 12.115

Figure 12.116

Figure 12.117

Determine the phase margin of a feedback network using this circuit with K = 1.

66.Repeat Problem 65 for K = 0:5.

67.In each case illustrated in Fig. 12.70, what happens if K is reduced by a factor of 2?

68.Suppose the amplifier in Example 12.41 is described by

Figure 12.118

where !p2 !p1. Compute the phase margin if the circuit is employed in a feedback system with K = 0:5.

69.Explain what happens to the characteristics illustrated in Fig. 12.72 if K drops by a factor of two. Assume !p1 and !p0 1 remain constant.

70.Figure 12.119 depicts the amplifier of Example 12.38 with a compensation capacitor added

CC

Figure 12.119

to node X. Explain how the circuit can be compensated for a phase margin of 45 .

Design Problems

In the following problems, unless otherwise stated, assume nCox = 2 pCox =

100 A=V2 and n = 0:5 p = 0:1 V,1.

71.Design the circuit of Example 12.15 for an open-loop gain of 50 and a nominal closed-loop gain of 4. Assume ISS = 0:5 mA. Choose R1 + R2 10(rO2jjrO4).

72.Design the circuit of Example 12.16 for an open-loop gain of 10, an closed-loop input impedance of 50 , and a nominal closed-loop gain of 2. Calculate the closed-loop I/O impedances. Assume R1 + R2 10RD.

73.Design the transimpedance amplifier of Example 12.18 for an open-loop gain of 10 k , a closed-loop gain of 1 k , a closed-loop input impedance of 50 , and a closed-loop output impedance of 200 . Assume RD1 = 1 k and RF is very large.

74.Repeat Problem 73 for the circuit shown in Fig. 12.94.

75.We wish to design the transimpedance amplifier depicted in Fig. 12.101 for a closed-loop gain of 1 k . Assume each transistor carries a collector bias current of 1 mA, = 100, VA = 1, and RF is very large.

(a) Determine the values of RC and RM for an open-loop gain of 20 k and an open-loop output impedance of 500 .

(b) Compute the required value of RF .

(c) Calculate the closed-loop I/O impedances.

76.Design the circuit illustrated in Fig. 12.105 for an open-loop voltage gain of 20, an openloop output impedance of 2 k , and a closed-loop voltage gain of 4. Assume = 0. Is the solution unique? If not, how should the circuit parameters be chosen to minimize the power dissipation?

77.Design the circuit of Fig. 12.107 for a closed-loop gain of 2, a tail current of 1 mA, and minimum output impedance. Assume = 100 and VA = 1.

78.Design the transimpedance amplifier of Fig. 12.111 for a closed-loop gain of 1 k and I/O impedances of 50 . Assume each transistor is biased at a collector current of 1 mA and

VA = 1.

SPICE Problems

In the following problems, use the MOS device models given in the Appendix I. For bipolar transistors, assume IS;npn = 5 10,16 A, npn = 100, VA;npn = 5 V, IS;pnp = 8 10,16 A, pnp = 50, VA;pnp = 3:5 V. Also, SPICE models the effect of charge storage in the base by a parameter called F = Cb=gm. Assume F (tf) = 20 ps.

79.Figure 12.120 shows a transimpedance amplifier often used in optical communications. Assume RF = 2 k .

VCC = 2.5 V

RC

Q 2

Vout

I in

Q 1 1 mA

RF

Figure 12.120

(a)Select the value of RC so that Q1 carries a bias current of 1 mA.

(b)Estimate the loop gain.

(c)Determine the closed-loop gain and I/O impedances.

(d)Determine the change in the closed-loop gain if VCC varies by 10%.

80.Figure 12.121 depicts another transimpedance amplifier, where the bias current of M1 is defined by the mirror arrangement ( M2 and M3). Assume W=L = 20 m=0:18 m for M1-M3.

VDD = 1.8 V

M 3 M 2

1 mA

RF

Vout

M 1

I in

Figure 12.121

(a)What value of RF yields a closed-loop gain of 1 k ?

(b)Determine the change in the closed-loop gain if VDD varies by 10%.

(c)Suppose the circuit drives a load capacitance of 100 fF. Verify that the input impedance exhibits inductive behavior and explain why.

81.In the circuit shown in Fig. 12.122, W=L = 20 m=0:18 m for M1 and M2.

(a)Determine the circuit's operating points for an input dc level of 0.9 V.

(b)Determine the closed-loop gain and I/O impedances.

82.In the circuit of Fig. 12.123, the three stages provide a high gain, approximating an op amp. Assume (W=L)1,6 = 10 m=0:18 m.

Figure 12.123

(a)Explain why the circuit is potentially unstable.

(b)Determine the step response and explain the circuit's behavior.

(c)Place a capacitor between nodes X and Y and adjust its value to obtain a well-behaved step response.

(d)Determine the gain error of the circuit with respect to the nominal value of 10.

83.In the three-stage amplifier of Fig. 12.124, (W=L)1,7 = 20 m=0:18 m.

Figure 12.124

(a)Determine the phase margin.

(b)Place a capacitor between nodes X and Y so as to obtain a phase margin of 60 . What is the unity-gain bandwidth under this condition?

(c)Repeat (b) if the compensation capacitor is tied between X and ground and compare the results.

References

1. B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill, 2001.

Output Stages and Power

Amplifiers

The amplifier circuits studied in previous chapters aim to achieve a high gain with desirable input and output impedance levels. However, many applications require circuits that can deliver a high power to the load. For example, the cellphone described in Chapter 1 must drive the antenna with 1 W of power. As another example, typical stereo systems deliver tens or hundreds of watts of audio power to speakers. Such circuits are called “power amplifiers” (PAs).

This chapter deals with circuits that can provide a high output power. We first reexamine circuits studied in previous chapters to understand their shortcomings for this task. Next, we introduce the “push-pull” stage and various modifications to improve its performance. The chapter outline is shown below.

13.1 General Considerations

The reader may wonder why the amplifier stages studied in previous chapters are not suited to high-power applications. Suppose we wish to deliver 1 W to an 8- speaker. Approximating the signal with a sinusoid of peak amplitude VP , we express the power absorbed by the speaker as

Also, the peak current flowing through the speaker is given by IP = VP =RL = 0:5 A.

We can make a number of important observations here. (1) The resistance that must be driven by the amplifier is much lower than the typical values (hundreds to thousands of ohms) seen

685

in previous chapters. (2) The current levels involved in this example are much greater than the typical currents (milliamperes) encountered in previous circuits. (3) The voltage swings delivered by the amplifier can hardly be viewed as “small” signals, requiring a good understanding of the large-signal behavior of the circuit. (4) The power drawn from the supply voltage, at least 1 W, is much higher than our typical values. (5) A transistor carrying such high currents and sustaining several volts (e.g., between collector and emitter) dissipates a high power and, as a result, heats up. High-power transistors must therefore handle high currents and high temperature.1

Based on the above observations, we can predict the parameters of interest in the design of power stages:

(1) “Distortion,” i.e., the nonlinearity resulting from large-signal operation. A high-quality audio amplifier must achieve a very low distortion so as to reproduce music with high fidelity. In previous chapters, we rarely dealt with distortion.

(2) “Power efficiency” or simply “efficiency,” denoted by

For example, a cellphone power amplifier that consumes 3 W from the battery to deliver 1 W to the antenna provides 33:3%. In previous chapters, the efficiency of circuits was of little concern because the absolute value of the power consumption was quite small (a few milliwatts).

(3) “Voltage rating.” As suggested by Eq. (13.1), higher power levels or load resistance values translate to large voltage swings and (possibly) high supply voltages. Also, the transistors in the output stage must exhibit breakdown voltages well above the output voltage swings.

13.2 Emitter Follower as Power Amplifier

With its relatively low output impedance, the emitter follower may be considered a good candidate for driving “heavy” loads, i.e., low impedances. As shown in Chapter 5, the small-signal gain of the follower is given by

We may therefore surmise that for, say, RL = 8 , a gain near unity can be obtained if 1=gm RL, e.g., 1=gm = 0:8 , requiring a collector bias current of 32.5 mA. We assume 1.

But, let us analyze the circuit's behavior in delivering large voltage swings (e.g. 4 VP ) to heavy loads. To this end, consider the follower shown in Fig. 13.1(a), where I1 serves as the bias current source. To simplify the analysis, we assume the circuit operates from negative and positive power supplies, allowing Vout to be centered around zero. For Vin 0:8 V, we have Vout 0 and IC 32:5 mA. If Vin rises from 0.8 V to 4.8 V, the emitter voltage follows the base voltage with a relatively constant difference of 0.8 V, producing a 4-V swing at the output [Fig. 13.1(b)].

Now suppose Vin begins from +0:8 V and gradually goes down [Fig. 13.1(c)]. We expect Vout to go below zero and hence part of I1 to flow from RL. For example, if Vin 0:7 V, then Vout ,0:1 V, and RL carries a current of 12.5 mA. That is, IC1 IE1 = 20 mA. Similarly, if Vin 0:6 V, then Vout ,0:2 V, IRL 25 mA, and hence IC1 7:5 mA. In other words, the collector current of Q1 continues to fall.

1And, in some applications, high voltages.

(d)

(c)

Figure 13.1 (a) Follower driving a heavy load, (b) input and output waveforms, (c) current path for as input becomes more negative, (d) current path as input becomes more positive.

What happens as Vin becomes more negative? Does Vout still track Vin? We observe that for a sufficiently low Vin, the collector current of Q1 drops to zero and RL carries the entire I1 [Fig. 13.1(d)]. For lower values of Vin, Q1 remains off and Vout = ,I1RL = ,260 mV.

Example 13.1

Solution

We have

688 Chap. 13 Output Stages and Power Amplifiers

Note from (13.6) that IC1 6:13 mA.

To determine the value of Vin that yields IC1 0:01I1 = 0:325 mA, we eliminate Vout from Eqs. (13.5) and (13.6):

Exercise

Repeat the above example if RL = 16 and I1 = 16 mA.

Let us summarize our thoughts thus far. In the arrangement of Fig. 13.1(a), the output tracks the input2 as Vin rises because Q1 can carry both I1 and the current drawn by RL. On the other hand, as Vin falls, so does IC1, eventually turning Q1 off and leading to a constant output voltage even though the input changes. As illustrated in the waveforms of Fig. 13.2(a), the output is severely distorted. From another perspective, the input/output characteristic of the cir-

Vout

0.8 V

Figure 13.2 (a) Distortion in a follower, (b) input/output characteristic.

cuit, depicted in Fig. 13.2(b), begins to substantially depart from a straight line as Vin falls below approximately 0.4 V (from Example 13.1).

Our foregoing study reveals that the follower of Fig. 13.1(a) cannot deliver voltage swings as large as 4 V to an 8- speaker. How can we remedy the situation? Noting that Vout;min = ,I1RL, we can increase I1 to greater than 50 mA so that for Vout = ,4 V, Q1 still remains on. This solution, however, yields a higher power dissipation and a lower efficiency.

13.3 Push-Pull Stage

Considering the operation of the emitter follower in the previous section, we postulate that the performance can be improved if I1 increases only when needed. In other words, we envision an arrangement wherein I1 increases as Vin becomes more negative and vice versa. Shown in Fig. 13.3(a) is a possible realization of this idea. Here, the constant current source is replaced with a

2The tracking may not be quite faithful because VBE experiences some change, but we ignore this effect for now.

Called the “push-pull” stage, this circuit merits a detailed study. We note that if Vin is sufficiently positive, Q1 operates as an emitter follower, Vout = Vin ,VBE1, and Q2 remains off [Fig. 13.3(b)] because its base-emitter junction is reverse-biased. By symmetry, if Vin is sufficiently negative, the reverse occurs [Fig. 13.3(c)] and Vout = Vin +jVBE2j. We say Q1 “pushes” current into RL in the former case and Q2 “pulls” current from RL in the latter.

Example 13.2

Sketch the input/output characteristic of the push-pull stage for very positive or very negative inputs.

Solution

As noted above,

That is, for negative inputs, Q2 shifts the signal up, and for positive inputs, Q1 shifts the signal down. Figure 13.4 plots the resulting characteristic.

Q 1 on

Vin

Q 2 on

Vin + VBE2

Figure 13.4 Push-pull stage characteristic.

Exercise

Repeat the above example for a CMOS output stage.

What happens as Vin approaches zero? The rough characteristic in Fig. 13.4 suggests that the two segments cannot meet if they must remain linear. In other words, the overall characteristic inevitably incurs nonlinearity and resembles that shown in Fig. 13.5, exhibiting a “dead zone” around Vin = 0.

Vin

Q 2 on

Vin + VBE2

Figure 13.5 Push-pull stage characteristic with dead zone.

Why does the circuit suffer from a dead zone? We make two observations. First, Q1 and Q2 cannot be on simultaneously: for Q1 to be on, Vin > Vout, but for Q2, Vin < Vout. Second, if Vin = 0, Vout must also be zero. This can be proved by contradiction. For example, if Vout > 0 (Fig. 13.6), then the current Vout=RL must be provided by Q1 (from VCC), requiring VBE1 > 0

VCC

Q 1

Vout > 0

Q 2 R L Vout

RL

VEE

Figure 13.6 Push-pull stage with zero input voltage.

and hence Vout = Vin , VBE1 < 0. That is, for Vin = 0, both transistors are off.

Now suppose Vin begins to increase from zero. Since Vout is initially at zero, Vin must reach at least VBE 600-700 mV before Q1 turns on. The output therefore remains at zero for Vin < 600 mV, exhibiting the dead zone depicted in Fig. 13.5. Similar observations apply to the dead zone for Vin < 0.

Example 13.3

Sketch the small-signal gain for the characteristic of Fig. 13.5 as a function of Vin.

Solution

The gain (slope) is near unity for very negative or positive inputs, falling to zero in the dead zone. Figure 13.7 plots the result.