Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

This rate is independent of the electric field but depends on the carrier temperature.

2.10.5  Mobility Modeling

Mobility modeling is divided into four categories: low field mobility, high field mobility, bulk semiconductor mobility, and inversion layer mobility. In low field mobility the carriers are in equilibrium with the lattice and the mobility is very low. This mobility is inversely related to the impurity scattering. The low field mobility models for bulk materials include constant mobility model, Caughey and Thomas model [27], Dorkel-Leturg model [28], Arora model [29], and Klaassen low-field mobility model [30]. The low field mobility is mainly affected by Coulomb scattering. In the high field case the mobility decreases with electric field as the high energy carriers take part in scattering and the mean drift velocity rises slowly with increasing electric field. Finally the drift velocity saturates to a constant value. The bulk mobility model is a three-step process. First the low field mobility is expressed as a function of lattice temperature and doping. Then the saturation velocity is expressed in terms of temperature. And finally the low and high field junction region is described. The mobility models can further be classified into physical based, semiempirical, and empirical models. As carriers move under the influence of an electric field, the velocity saturates and so the effective mobility reduces because the drift velocity is equal to the product of mobility and the electric field. The field-dependent mobility expressions of Caughey and Thomas [27] are

where n0 and p0 are the respective low field electron and hole mobility, and E is the parallel electric field. The saturation velocities are calculated

from the temperature-dependent model in [31] as

2.11  Introduction to MOS Transistor

The most important requirement for a field-effect transistor (FET) is zero or negligible gate leakage current. It is important to isolate the gate from the channel so that no current flows into the gate. One needs some kind of barrier for the electron (or hole) from the gate to the source, the channel, and the drain. In MOSFET, an insulator provides the barrier. It is possible to grow a high-quality and reliable insulator using Silicon (Si). SiO2 is stable and makes a firm bonding with Silicon. This oxide makes selective diffusion and easy pattern transfer. This has led to the well-established silicon MOSFET technology to become dominant. In MOSFET application of a large gate bias inverts the bands and induces the electrons (or holes) in a channel without the gate leakage. Over the last few years steady progress has been made on using the MOSFET concept with other semiconductors, notably (Gallium Arsenide) GaAs. GaAs n-MOSFETs have channel mobilities much higher than those in n-MOSFET based on the silicon as in [32]. However, GaAs technology does not provide a high-quality oxide. Thus, the widespread use of such devices is still not prevalent because of lack of good-quality oxide.

The Si technology is unique in the sense that a high-quality oxide SiO2 can be formed on the silicon wafer. The Si-SiO2 interface perfection is required for a field-effect device. Their higher areal density, better switching characteristics, and lower power dissipation have made them the dominant device in electronic systems.

There are two basic types of MOS transistors: the n-channel and the p-channel. A circuit containing only n-channel devices is produced by an nMOS process. Similarly, a pMOS process fabricates circuits that contain only p-channel transistors.

2.12  Structure and Symbol of MOSFET

The structure of an n-channel MOS transistor is shown in Figure 2.19(a), consisting of two n-type regions embedded in a p-type substrate, connected via metal or polysilicon to external conductors called the source and the drain.

FIGURE 2.19

(a) An n-type NMOS device structure. (b) Symbol of MOSFET.

The symbol of MOSFET is shown in Figure 2.19(b). An n-channel MOS transistor is fabricated in a p-type semiconductor substrate, usually silicon [33]. Two n-type regions are made in the substrate and the current flows between these two regions. The region with the lowest applied potential is called the source and that with the highest potential is called the drain. On the surface, a thin silicon dioxide (SiO2) layer is formed and on top of this a conducting polysilicon material called a gate is deposited. An electron-rich layer called a channel can be created between the source and the drain underneath the gate when a positive gate bias is applied. When appropriate voltages are applied at the source and the drain, electrons can flow from the source into the drain. If the substrate material is n-type and the diffused regions are p-type, a similar structure will represent a p-channel MOS transistor. The gate plate must act as a good conductor and was in fact realized by metals like aluminum in the early generations of the MOS technology. However, it was discovered that the non-crystalline polysilicon exhibits better fabrication and physical properties. The bonding between the silicon substrate and polysilicon gate is better than that between the metal gate and the silicon substrate. Thus the metal M is replaced by a heavily doped polysilicon.

Here L and W denote the length and width of the channel, respectively. In the most common mode of operation of the transistor, the source and the substrate are grounded and the drain is connected to a supply voltage VDD through a load resistor, which is positive for an n-channel transistor and negative for a p-channel transistor. In a MOSFET the channel charge is induced electrostatically by the gate by using it as a capacitor without the need for doping.

2.13  Basic Operation of MOSFET

2.13.1  Operation of MOSFET with Zero Gate Voltage

Let us consider the gate voltage equal to zero while the p-type substrate

and the source are grounded (VSub = VS = 0) [34]. The drain is connected to a positive voltage source. Because the source and the substrate are at the

same potential, no current flows in the source-substrate junction. The drainsubstrate junction is reverse biased, and except for a small reverse leakage current, no current flows in that junction. These back-to-back diodes prevent current conduction from the source to the drain, as in Figure 2.20(a). The depletion formation is shown in Figure 2.20(b). The MOSFET has a very high resistance between the source and the drain. It is operating in the “cut off” as there is no conducting channel between the source and the drain. Small current flows due to the second-order effect under the weak inversion, called subthreshold current.

2.13.2  Operation of MOSFET with a Positive Gate Voltage

In this case a constant positive bias is applied to the gate as in Figure 2.21(a). There is no gate current because the metal electrode is insulated from the silicon. However, the positively biased gate electrode attracts electrons from the semiconductor, and an electron-rich layer forms underneath the gate insulator. In effect, negative charges are induced in the underlying Si by the formation of a depletion region and a thin surface region containing mobile electrons.

FIGURE 2.26

Energy band diagram of MOSFET: (a) flat band, (b) accumulation, (c) depletion, and (d) inversion.

2.14.1  Accumulation of Holes

When a negative bias is applied between the metal and the semiconductor, a negative surface charge is deposited on the metal at the metal oxide interface, and the structure behaves as a parallel-plate capacitor whose electrodes are the silicon and the metal, with oxide as the insulator [39]. In response an equal net positive charge appears at the surface of the semiconductor at the silicon-oxide interface. This silicon charge whose thickness is approximately 10 nm can also be considered as a surface charge. This hole-rich thin layer is called an accumulation layer.

The energy band diagrams are drawn for negative charges, whereas an electrostatic potential diagram is drawn for positive test charges. In metal, application of negative bias reduces the electrostatic potential, and as a result electron energies are raised in the metal relative to the semiconductor. The Fermi level for the metal rises above its equilibrium position by qV, where V