STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Table 45.

DAC characteristics

Symbol

Parameter

Min

Typ

Max(1)

Unit

Comments

VDDA

Analog supply voltage

2.4

3.6

V

VREF+

Reference supply voltage

2.4

3.6

V

VREF+ must always be below

VDDA

VSSA

Ground

0

0

V

(2)

Resistive load with buffer ON

5

k

RLOAD

When the buffer is OFF, the

R (1)

Impedance output with buffer OFF

15

k

Minimum resistive load between

O

DAC_OUT and VSS to have a

1% accuracy is 1.5 M

(1)

Maximum capacitive load at

Capacitive load

50

pF

DAC_OUT pin (when the buffer

CLOAD

is ON).

DAC_OUT

Lower DAC_OUT voltage with buffer

It gives the maximum output

0.2

V

excursion of the DAC.

min(1)

ON

It corresponds to 12-bit input

code (0x0E0) to (0xF1C) at

DAC_OUT

Higher DAC_OUT voltage with buffer

VDDA –

V

V

REF+

= 3.6 V and (0x155) and

max(1)

ON

0.2

(0xEAB) at VREF+ = 2.4 V

DAC_OUT

Lower DAC_OUT voltage with buffer

0.5

mV

min(1)

OFF

It gives the maximum output

DAC_OUT

Higher DAC_OUT voltage with buffer

VREF+

V

excursion of the DAC.

max(1)

OFF

– 1LSB

With no load, worst code

IDDVREF+

DAC DC current consumption in

220

µA

(0xF1C) at VREF+ = 3.6 V in

quiescent mode (Standby mode)

terms of DC consumption on the

inputs

380

µA

With no load, middle code

(0x800) on the inputs

DAC DC current consumption in

IDDA

With no load, worst code

quiescent mode (Standby mode)

480

µA

(0xF1C) at VREF+ = 3.6 V in

terms of DC consumption on the

inputs

±0.5

LSB

Given for the DAC in 10-bit

Differential non linearity Difference

configuration

DNL(3)

between two consecutive code-1LSB)

±2

LSB

Given for the DAC in 12-bit

configuration

Integral non linearity (difference

±1

LSB

Given for the DAC in 10-bit

between measured value at Code i

configuration

INL(3)

and the value at Code i on a line

Given for the DAC in 12-bit

drawn between Code 0 and last Code

±4

LSB

1023)

configuration

Doc ID 16455 Rev 3

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Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 45.

DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max(1)

Unit

Comments

±10

mV

Given for the DAC in 12-bit

configuration

Offset error

Offset(3)

(difference between measured value

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

at Code (0x800) and the ideal value =

VREF+/2)

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

Gain

Gain error

±0.5

%

Given for the DAC in 12bit

error(3)

configuration

Settling time (full scale: for a 10-bit

(

input code transition between the

tSETTLING

lowest and the highest input codes

3

4

µs

CLOAD

50 pF, RLOAD 5 k

3)

when DAC_OUT reaches final value

±1LSB

Max frequency for a correct

Update

DAC_OUT change when small

1

MS/s

CLOAD

50 pF, RLOAD 5 k

(3)

variation in the input code (from code i

rate

to i+1LSB)

(3)

Wakeup time from off state (Setting

CLOAD

50 pF, RLOAD 5 k

the ENx bit in the DAC Control

6.5

10

µs

input code between lowest and

tWAKEUP

register)

highest possible ones.

PSRR+ (1)

Power supply rejection ratio (to VDDA)

–67

–40

dB

No R

, C

LOAD

= 50 pF

(static DC measurement

LOAD

Buffer(1)

R LOAD

12-bit

DACx_OUT

digital to

analog

converter

C LOAD

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Doc ID 16455 Rev 3

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Table 46.

TS characteristics

Symbol

Parameter

Min

Typ

Max

Unit

TL(1)

VSENSE linearity with temperature

1

2

°C

Avg_Slope(1)

Average slope

4.0

4.3

4.6

mV/°C

V25(1)

Voltage at 25°C

1.32

1.41

1.50

V

(2)

Startup time

4

10

µs

tSTART

(3)(2)

ADC sampling time when reading the temperature

17.1

µs

TS_temp

Doc ID 16455 Rev 3

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