NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

Simulating the Design

You are now ready to begin simulating.

1.To simulate, click the Run Simulation button on the SimControl window.

Simulation will stop almost immediately as the signal out_p1 is initialized to a value of

00000000. Notice that both of the signals that you are monitoring in the Watch Window are highlighted. This indicates that the value of the signals has changed since the simulator was last stopped.

2.Click the Run Simulation button again. The Run Simulation button changes to the Stop Simulation button when simulation starts.

The simulation proceeds for a few moments as the simulator runs through the decoding process for signal out_p1. Notice the time update in the SimControl window just under the Tool Bar. The breakpoint should execute around 3.16 ms. Note that the waveforms update dynamically in Signalscan waves as the simulation runs.

When the object breakpoint executes again, notice that, in the Watch Window, load_digit and out_p1 do not match.

3.Click the Run Simulation button one more time.

The simulation is automatically stopped by a $stop call in the testbench. The SimControl window reports that the digit found was a 2 and that the simulation failed because the first expected digit was 1.

Tracing Back Signals

You will now use the Signal Flow Browser (SFB) to trace back the drivers on the output signal out_p1. The SFB lets you trace backwards through a design from a signal that has a questionable value to where a signal first diverges from expected behavior.

1.Select the signal out_p1 in the Watch Window.

2.Click on the Signal Flow Browser button on the Watch Window Tool Bar.

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

The SFB displays signal out_p1 and its driver(s). In this case, the driver is coming from instance RESULTS_CONV_INST.

If you prefer to see the information in the SFB displayed in a tree representation instead of the default stack view, select View—Tree Display.

3.Select the results_conv box and press and hold the right mouse button to display the pop-up menu. Select Descend to descend into this instance.

You will now see the driver out_p1 inside of this instance.

4.Select this box and then press and hold the right mouse button to display the pop-up menu. Select Show Drivers and Assignments.

You can now see all of the drivers for signal out_p1. The digit that you expected to find for out_p1 was 1 but you found 2 instead. Notice that out_p1 is being driven by two values called val_key_2, but none called val_key_1.

5.Select the first driver box.

This shows you the source code in the SimControl window for this driver. If you scroll up in the Source Browser a few lines, you can see that this is a case statement. The first two statements both assign the same value, val_key_2. The first line should assign val_key_1.

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

Editing a Source File

To correct this problem in the source file:

1.Select File—Edit Source in SimControl.

The Edit File form appears. The form is seeded with the source file to open and the line number to go to.

2.Click the OK button to open the source code file and go to the indicated line number.

Note: Not all editors can identify line numbers. With some editors, such as Microsoft

WordPad, you may go to the first line of the file instead of to the specified line. If this happens, search for the case statement to get to the desired line of code.

3.Correct the source line as indicated by the comment in the file, save the results, and exit the editor.

4.Compile, elaborate, and reload the simulation snapshot. To do this automatically from the SimControl window, select File—Reinvoke.

When you reinvoke, the SimControl window temporarily disappears. An OS shell displays the compilation and elaboration, and the snapshot is then automatically loaded into the simulator. Your complete debug environment is restored, including the probed waveform database and the object breakpoint on out_p1.

Setting a Line Breakpoint

In this and the following sections, you will modify the breakpoints that you have already set and look at some different ways to stop the simulation. You will now navigate the design to the level at which you will set a line breakpoint.

1.Use the Navigator to traverse through the hierarchy to test.top.RESULTS_CONV_INST.

The source code for this module appears in the SimControl Source Browser.

2.On the SimControl window, select File—Find—Line. Enter a value of 256 and click the OK button.

This takes you to line 256 in the source file, which is the case statement that you modified in the previous section.

3.To set a line breakpoint, double-click on the line number for this statement. This will set a red breakpoint icon next to the line number.

Note: To set the line breakpoint, make sure that you click on the line number, not the

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

source code line.

Disabling a Breakpoint

Now you can remove the object breakpoint that you set on out_p1.

1.Select Show—Breakpoints in the SimControl window.

The Debug Settings form appears. The form lists the object breakpoint and the line breakpoint.

2.Select the check next to the object breakpoint to disable the breakpoint.

3.Select File—Close to close the form.

Setting a Condition Breakpoint

Now set a condition breakpoint on out_p1. Rather than setting a breakpoint that occurs on any transition of out_p1, you will set a condition breakpoint that triggers only when this signal transitions to the value of load_digit. The first value load_digit gets is 00110001.

1.Select the signal out_p1 in the Watch Window.

2.Select Full Name from the right mouse button pop-up menu.

This shows you the full hierarchical name of the signal. You will need this full name when creating a Tcl expression for the condition breakpoint.

3.Select Set—Breakpoint—Condition.

4.Enter the following expression in the condition field:

#test.out_p1 = 8’b00110001

The # translates the signal test.out_p1 to its simulation value. The syntax of the value being searched for is the same as regular Verilog language syntax (8’b00110001).

5.Click the OK button to set the breakpoint.

Notice the stop command in the SimControl console window.

Simulating the Modified Design

1.Click the Run Simulation button in SimControl.

It will take a moment for the simulation to hit the line breakpoint at about 3.16 ms. When the line breakpoint executes, the SimControl source code debugger jumps to the line on